/*
 *  Motorola MCF5206[e] ColdFire System Integration Module Header
 *
 *  Header file for the Motorola ColdFire MCF5206[e] internal modules.
 *  This contains a structure which can be used to access internal
 *  MCF5206[e] modules easily as well as bit pattern definitions for
 *  most registers.
 *
 *  This file was compiled from MCF5206UM/AD, MCF5206eUM/AD
 *  and SBC5206 eval board monitor source.
 *
 *  The MCF5206e support is enabled by defining MCF5206E
 *
 *  Author:
 *    David Fiddes, D.J@fiddes.net
 *    http://fiddes.net/coldfire/
 *
 *  This code has no copyright and may freely be used in whatever 
 *  manner you see fit.
 *
 *  THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY 
 *  OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT    
 *  LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR    
 *  FITNESS FOR A PARTICULAR PURPOSE.                              
 */
 
#ifndef __MCF5206_H
#define __MCF5206_H

/*
 * Cache and Access Control Register routines and defintions
 */
#define MCF5206_CACR_CENB       (0x80000000)
#define MCF5206_CACR_CFRZ       (0x08000000)
#define MCF5206_CACR_CINV       (0x01000000)
#define MCF5206_CACR_CMOD       (0x00000200)
#define MCF5206_CACR_CWRP       (0x00000020)
#define MCF5206_CACR_CLNF_00    (0x00000000)
#define MCF5206_CACR_CLNF_01    (0x00000001)
#define MCF5206_CACR_CLNF_10    (0x00000002)
#define MCF5206_CACR_DBWE       (0x00000100)

#define MCF5206_ACR_BASE(a)     ((a)&0xFF000000)
#define MCF5206_ACR_MASK(a)     (((a)&0xFF000000) >> 8)
#define MCF5206_ACR_EN          (0x00008000)
#define MCF5206_ACR_S_USER      (0x00000000)
#define MCF5206_ACR_S_SUPER     (0x00002000)
#define MCF5206_ACR_S_IGNORE    (0x00006000)
#define MCF5206_ACR_ENIB        (0x00000080)
#define MCF5206_ACR_CM          (0x00000040)
#define MCF5206_ACR_WP          (0x00000004)
#define MCF5206_ACR_BUFW        (0x00000020)

#define MCF5206_SRAMBAR_BASE(a) ((a)&0xFFFFFE00)
#define MCF5206_SRAMBAR_WP      (0x00000100)
#define MCF5206_SRAMBAR_AS_CI   (0x00000080)
#define MCF5206_SRAMBAR_AS_SC   (0x00000040)
#define MCF5206_SRAMBAR_AS_SD   (0x00000020)
#define MCF5206_SRAMBAR_AS_UC   (0x00000004)
#define MCF5206_SRAMBAR_AS_UD   (0x00000002)
#define MCF5206_SRAMBAR_V       (0x00000001)

#define MCF5206_MBAR_BASE(a)    ((a)&0xFFFFFC00)
#define MCF5206_MBAR_SC         (0x00000010)
#define MCF5206_MBAR_SD         (0x00000008)
#define MCF5206_MBAR_UC         (0x00000004)
#define MCF5206_MBAR_UD         (0x00000002)
#define MCF5206_MBAR_V          (0x00000001)

 
typedef struct
{
  unsigned16 csar;        /* Chip-Select X Base Address Register, 16-bit, R/W (00-01) */
  unsigned8  pack01[2];   /* 02-03 */
  unsigned32 csmr;        /* Chip-Select X Address Mask Register, 32-bit, R/W (04-07) */
  unsigned8  pack02[2];   /* 08-09 */
  unsigned16 cscr;        /* Chip-Select X Control Register, 16-bit, R/W (0A-0B) */
} csstruct;


#define MCF5206_TIMER_TMR_PS(a)     (((a)&0x00FF)<<8)
#define MCF5206_TIMER_TMR_CE_ANY    (0x00C0)
#define MCF5206_TIMER_TMR_CE_RISE   (0x0080)
#define MCF5206_TIMER_TMR_CE_FALL   (0x0040)
#define MCF5206_TIMER_TMR_CE_NONE   (0x0000)
#define MCF5206_TIMER_TMR_OM        (0x0020)
#define MCF5206_TIMER_TMR_ORI       (0x0010)
#define MCF5206_TIMER_TMR_FRR       (0x0008)
#define MCF5206_TIMER_TMR_CLK_TIN   (0x0006)
#define MCF5206_TIMER_TMR_CLK_DIV16 (0x0004)
#define MCF5206_TIMER_TMR_CLK_MSCLK (0x0002)
#define MCF5206_TIMER_TMR_CLK_STOP  (0x0000)
#define MCF5206_TIMER_TMR_RST       (0x0001)

#define MCF5206_TIMER_TER_REF       (0x02)
#define MCF5206_TIMER_TER_CAP       (0x01)


/* ColdFire version independent versions */
#define MCF5XXX_TIMER_TMR_PS(a)     MCF5206_TIMER_TMR_PS(a)
#define MCF5XXX_TIMER_TMR_CE_ANY    MCF5206_TIMER_TMR_CE_ANY
#define MCF5XXX_TIMER_TMR_CE_FALL   MCF5206_TIMER_TMR_CE_FALL
#define MCF5XXX_TIMER_TMR_CE_RISE   MCF5206_TIMER_TMR_CE_RISE
#define MCF5XXX_TIMER_TMR_CE_NONE   MCF5206_TIMER_TMR_CE_NONE
#define MCF5XXX_TIMER_TMR_OM        MCF5206_TIMER_TMR_OM
#define MCF5XXX_TIMER_TMR_ORI       MCF5206_TIMER_TMR_ORI   
#define MCF5XXX_TIMER_TMR_FRR       MCF5206_TIMER_TMR_FRR 
#define MCF5XXX_TIMER_TMR_CLK_TIN   MCF5206_TIMER_TMR_CLK_TIN
#define MCF5XXX_TIMER_TMR_CLK_DIV16 MCF5206_TIMER_TMR_CLK_DIV16
#define MCF5XXX_TIMER_TMR_CLK_MSCLK MCF5206_TIMER_TMR_CLK_MSCLK
#define MCF5XXX_TIMER_TMR_CLK_STOP  MCF5206_TIMER_TMR_CLK_STOP
#define MCF5XXX_TIMER_TMR_RST       MCF5206_TIMER_TMR_RST

#define MCF5XXX_TIMER_TER_REF       MCF5206_TIMER_TER_REF
#define MCF5XXX_TIMER_TER_CAP       MCF5206_TIMER_TER_CAP  

typedef struct
{
  unsigned16 tmr;         /* TIMERx Mode Register, 16-bit, R/W (00-01) */
  unsigned8  pack01[2];   /* 02-03 */
  unsigned16 trr;         /* TIMERx Mode Register, 16-bit, R/W (04-05) */
  unsigned8  pack02[2];   /* 06-07 */
  unsigned16 tcr;         /* TIMERx Capture Register, 16-bit, R (08-09) */
  unsigned8  pack03[2];   /* 0A-0B */
  unsigned16 tcn;         /* TIMERx Counter, 16-bit, R/W (0C-0D) */
  unsigned8  pack04[3];   /* 0E-10 */
  unsigned8  ter;         /* TIMERx Event Register, 8-bit, R/W (11) */
} tmrstruct;
  

#define MCF5206_UART_UMR1_RXRTS         (0x80)
#define MCF5206_UART_UMR1_RXIRQ         (0x40)
#define MCF5206_UART_UMR1_ERR           (0x20)
#define MCF5206_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5206_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5206_UART_UMR1_PM_NONE       (0x10)
#define MCF5206_UART_UMR1_PM_FORCE_HI   (0x0C)
#define MCF5206_UART_UMR1_PM_FORCE_LO   (0x08)
#define MCF5206_UART_UMR1_PM_ODD        (0x04)
#define MCF5206_UART_UMR1_PM_EVEN       (0x00)
#define MCF5206_UART_UMR1_BC_5          (0x00)
#define MCF5206_UART_UMR1_BC_6          (0x01)
#define MCF5206_UART_UMR1_BC_7          (0x02)
#define MCF5206_UART_UMR1_BC_8          (0x03)

#define MCF5206_UART_UMR2_CM_NORMAL     (0x00)
#define MCF5206_UART_UMR2_CM_ECHO       (0x40)
#define MCF5206_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5206_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define MCF5206_UART_UMR2_TXRTS         (0x20)
#define MCF5206_UART_UMR2_TXCTS         (0x10)
#define MCF5206_UART_UMR2_STOP_BITS_1   (0x07)
#define MCF5206_UART_UMR2_STOP_BITS_15  (0x08)
#define MCF5206_UART_UMR2_STOP_BITS_2   (0x0F)

#define MCF5206_UART_USR_RB             (0x80)
#define MCF5206_UART_USR_FE             (0x40)
#define MCF5206_UART_USR_PE             (0x20)
#define MCF5206_UART_USR_OE             (0x10)
#define MCF5206_UART_USR_TXEMP          (0x08)
#define MCF5206_UART_USR_TXRDY          (0x04)
#define MCF5206_UART_USR_FFULL          (0x02)
#define MCF5206_UART_USR_RXRDY          (0x01)

#define MCF5206_UART_UCSR_9600_BPS      (0xBB)
#define MCF5206_UART_UCSR_19200_BPS     (0xCC)

#define MCF5206_UART_UCR_NONE           (0x00)
#define MCF5206_UART_UCR_STOP_BREAK     (0x70)
#define MCF5206_UART_UCR_START_BREAK    (0x60)
#define MCF5206_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5206_UART_UCR_RESET_ERROR    (0x40)
#define MCF5206_UART_UCR_RESET_TX       (0x30)
#define MCF5206_UART_UCR_RESET_RX       (0x20)
#define MCF5206_UART_UCR_RESET_MR       (0x10)
#define MCF5206_UART_UCR_TX_DISABLED    (0x08)
#define MCF5206_UART_UCR_TX_ENABLED     (0x04)
#define MCF5206_UART_UCR_RX_DISABLED    (0x02)
#define MCF5206_UART_UCR_RX_ENABLED     (0x01)

#define MCF5206_UART_UIPCR_COS          (0x10)
#define MCF5206_UART_UIPCR_CTS          (0x01)

#define MCF5206_UART_UACR_BRG           (0x80)
#define MCF5206_UART_UACR_CTMS_TIMER    (0x60)
#define MCF5206_UART_UACR_IEC           (0x01)

#define MCF5206_UART_UISR_COS           (0x80)
#define MCF5206_UART_UISR_DB            (0x04)
#define MCF5206_UART_UISR_RXRDY         (0x02)
#define MCF5206_UART_UISR_TXRDY         (0x01)

#define MCF5206_UART_UIMR_COS           (0x80)
#define MCF5206_UART_UIMR_DB            (0x04)
#define MCF5206_UART_UIMR_FFULL         (0x02)
#define MCF5206_UART_UIMR_TXRDY         (0x01)


/* ColdFire version independent versions */
#define MCF5XXX_UART_UMR1_RXRTS           MCF5206_UART_UMR1_RXRTS
#define MCF5XXX_UART_UMR1_RXIRQ           MCF5206_UART_UMR1_RXIRQ
#define MCF5XXX_UART_UMR1_ERR             MCF5206_UART_UMR1_ERR
#define MCF5XXX_UART_UMR1_PM_MULTI_ADDR   MCF5206_UART_UMR1_PM_MULTI_ADDR
#define MCF5XXX_UART_UMR1_PM_MULTI_DATA   MCF5206_UART_UMR1_PM_MULTI_DATA
#define MCF5XXX_UART_UMR1_PM_NONE         MCF5206_UART_UMR1_PM_NONE
#define MCF5XXX_UART_UMR1_PM_FORCE_HI     MCF5206_UART_UMR1_PM_FORCE_HI
#define MCF5XXX_UART_UMR1_PM_FORCE_LO     MCF5206_UART_UMR1_PM_FORCE_LO
#define MCF5XXX_UART_UMR1_PM_ODD          MCF5206_UART_UMR1_PM_ODD
#define MCF5XXX_UART_UMR1_PM_EVEN         MCF5206_UART_UMR1_PM_EVEN
#define MCF5XXX_UART_UMR1_BC_5            MCF5206_UART_UMR1_BC_5
#define MCF5XXX_UART_UMR1_BC_6            MCF5206_UART_UMR1_BC_6
#define MCF5XXX_UART_UMR1_BC_7            MCF5206_UART_UMR1_BC_7
#define MCF5XXX_UART_UMR1_BC_8            MCF5206_UART_UMR1_BC_8

#define MCF5XXX_UART_UMR2_CM_NORMAL       MCF5206_UART_UMR2_CM_NORMAL
#define MCF5XXX_UART_UMR2_CM_ECHO         MCF5206_UART_UMR2_CM_ECHO
#define MCF5XXX_UART_UMR2_CM_LOCAL_LOOP   MCF5206_UART_UMR2_CM_LOCAL_LOOP
#define MCF5XXX_UART_UMR2_CM_REMOTE_LOOP  MCF5206_UART_UMR2_CM_REMOTE_LOOP
#define MCF5XXX_UART_UMR2_TXRTS           MCF5206_UART_UMR2_TXRTS
#define MCF5XXX_UART_UMR2_TXCTS           MCF5206_UART_UMR2_TXCTS
#define MCF5XXX_UART_UMR2_STOP_BITS_1     MCF5206_UART_UMR2_STOP_BITS_1
#define MCF5XXX_UART_UMR2_STOP_BITS_15    MCF5206_UART_UMR2_STOP_BITS_15
#define MCF5XXX_UART_UMR2_STOP_BITS_2     MCF5206_UART_UMR2_STOP_BITS_2
#define MCF5XXX_UART_UMR2_STOP_BITS(a)    MCF5206_UART_UMR2_STOP_BITS(a)

#define MCF5XXX_UART_USR_RB               MCF5206_UART_USR_RB
#define MCF5XXX_UART_USR_FE               MCF5206_UART_USR_FE
#define MCF5XXX_UART_USR_PE               MCF5206_UART_USR_PE
#define MCF5XXX_UART_USR_OE               MCF5206_UART_USR_OE
#define MCF5XXX_UART_USR_TXEMP            MCF5206_UART_USR_TXEMP
#define MCF5XXX_UART_USR_TXRDY            MCF5206_UART_USR_TXRDY
#define MCF5XXX_UART_USR_FFULL            MCF5206_UART_USR_FFULL
#define MCF5XXX_UART_USR_RXRDY            MCF5206_UART_USR_RXRDY  

#define MCF5XXX_UART_UCSR_9600_BPS        MCF5206_UART_UCSR_9600_BPS
#define MCF5XXX_UART_UCSR_RCS(a)          MCF5206_UART_UCSR_RCS(a)
#define MCF5XXX_UART_UCSR_TCS(a)          MCF5206_UART_UCSR_TCS(a)

#define MCF5XXX_UART_UCR_NONE             MCF5206_UART_UCR_NONE
#define MCF5XXX_UART_UCR_STOP_BREAK       MCF5206_UART_UCR_STOP_BREAK
#define MCF5XXX_UART_UCR_START_BREAK      MCF5206_UART_UCR_START_BREAK
#define MCF5XXX_UART_UCR_RESET_BKCHGINT   MCF5206_UART_UCR_RESET_BKCHGINT 
#define MCF5XXX_UART_UCR_RESET_ERROR      MCF5206_UART_UCR_RESET_ERROR
#define MCF5XXX_UART_UCR_RESET_TX         MCF5206_UART_UCR_RESET_TX
#define MCF5XXX_UART_UCR_RESET_RX         MCF5206_UART_UCR_RESET_RX
#define MCF5XXX_UART_UCR_RESET_MR         MCF5206_UART_UCR_RESET_MR
#define MCF5XXX_UART_UCR_TX_DISABLED      MCF5206_UART_UCR_TX_DISABLED
#define MCF5XXX_UART_UCR_TX_ENABLED       MCF5206_UART_UCR_TX_ENABLED
#define MCF5XXX_UART_UCR_RX_DISABLED      MCF5206_UART_UCR_RX_DISABLED
#define MCF5XXX_UART_UCR_RX_ENABLED       MCF5206_UART_UCR_RX_ENABLED

#define MCF5XXX_UART_UIPCR_COS            MCF5206_UART_UIPCR_COS
#define MCF5XXX_UART_UIPCR_CTS            MCF5206_UART_UIPCR_CTS

#define MCF5XXX_UART_UACR_BRG             MCF5206_UART_UACR_BRG
#define MCF5XXX_UART_UACR_CTMS_TIMER      MCF5206_UART_UACR_CTMS_TIMER
#define MCF5XXX_UART_UACR_IEC             MCF5206_UART_UACR_IEC

#define MCF5XXX_UART_UISR_COS             MCF5206_UART_UISR_COS
#define MCF5XXX_UART_UISR_DB              MCF5206_UART_UISR_DB
#define MCF5XXX_UART_UISR_RXRDY           MCF5206_UART_UISR_RXRDY
#define MCF5XXX_UART_UISR_TXRDY           MCF5206_UART_UISR_TXRDY

#define MCF5XXX_UART_UIMR_COS             MCF5206_UART_UIMR_COS
#define MCF5XXX_UART_UIMR_DB              MCF5206_UART_UIMR_DB 
#define MCF5XXX_UART_UIMR_FFULL           MCF5206_UART_UIMR_FFULL
#define MCF5XXX_UART_UIMR_TXRDY           MCF5206_UART_UIMR_TXRDY

#define MCF5XXX_UART_UIP_CTS              MCF5206_UART_UIP_CTS 

#define MCF5XXX_UART_UOP_RTS              MCF5206_UART_UOP_RTS 
#define MCF5XXX_UART_UOP0_RTS             MCF5206_UART_UOP0_RTS   


typedef struct
{
  unsigned8 umr;          /* UARTx Mode Register, 8-bit, R/W (00) */
  unsigned8 pack01[3];    /* 01-03 */
  unsigned8 usr;          /* UARTx Status Register, 8-bit, R (04) */
  unsigned8 pack02[7];    /* 05-0B */
  unsigned8 urbuf;        /* UARTx Receiver Buffer, 8-bit, R (0C) */
  unsigned8 pack03[3];    /* 0D-0F */
  unsigned8 uipcr;        /* UARTx Input Port Change Register, 8-bit, R (10) */
  unsigned8 pack04[3];    /* 11-13 */
  unsigned8 uisr;         /* UARTx Interrupt Status Register, 8-bit, R (14) */
  unsigned8 pack05[3];    /* 15-17 */
  unsigned8 ubg1;         /* UARTx Baud Rate Generator PreScale MSB, 8-bit, R/W (18) */
  unsigned8 pack06[3];    /* 19-1B */
  unsigned8 ubg2;         /* UARTx Baud Rate Generator PreScale LSB, 8-bit, R/W (1C) */
  unsigned8 pack07[19];   /* 1D-2F */
  unsigned8 uivr;         /* UARTx Interrupt Vector Register, 8-bit, R/W (30) */
  unsigned8 pack08[3];    /* 31-33 */
  unsigned8 uip;          /* UARTx Input Port Register, 8-bit, R (34) */
} UARTReadStruct;

typedef struct
{
  unsigned8 umr;          /* UARTx Mode Register, 8-bit, R/W (00) */
  unsigned8 pack01[3];    /* 01-03 */
  unsigned8 ucsr;         /* UART1 Clock Select Register, 8-bit, W (04) */
  unsigned8 pack02[3];    /* 05-07 */
  unsigned8 ucr;          /* UARTx Command Register, 8-bit, W (08) */
  unsigned8 pack2a[3];    /* 09-0B */
  unsigned8 utbuf;        /* UARTx Transmitter Buffer, 8-bit, W (0C) */
  unsigned8 pack03[3];    /* 0D-0F */
  unsigned8 uacr;         /* UARTx Auxiliary Control Register, 8-bit, W (10) */
  unsigned8 pack04[3];    /* 11-13 */
  unsigned8 uimr;         /* UARTx Interrupt Mask Register, 8-bit, W (14) */
  unsigned8 pack05[3];    /* 15-17 */
  unsigned8 ubg1;         /* UARTx Baud Rate Generator PreScale MSB, 8-bit, R/W (18) */
  unsigned8 pack06[3];    /* 19-1B */
  unsigned8 ubg2;         /* UARTx Baud Rate Generator PreScale LSB, 8-bit, R/W (1C) */
  unsigned8 pack07[19];   /* 1D-2F */
  unsigned8 uivr;         /* UARTx Interrupt Vector Register, 8-bit, R/W (30) */
  unsigned8 pack08[7];    /* 31-37 */
  unsigned8 uop1;         /* UARTx Output Port Bit Set Command, 8-bit, W (38) */
  unsigned8 pack09[3];    /* 39-3B */
  unsigned8 uop0;         /* UARTx Output Port Bit Reset Command, 8-bit, W (3C) */
} UARTWriteStruct;

typedef union
{
  UARTReadStruct  read;
  UARTWriteStruct write; 
  unsigned8 pack01[0x40];  
} uartstruct;


#define MCF5206_MBUS_MADR_ADDR(a) ((a)&0xFE)

#define MCF5206_MBUS_MFDR_MBC(a)  ((a)&0x3F)

#define MCF5206_MBUS_MBCR_MEN     (0x80)
#define MCF5206_MBUS_MBCR_MIEN    (0x40)
#define MCF5206_MBUS_MBCR_MSTA    (0x20)
#define MCF5206_MBUS_MBCR_MTX     (0x10)
#define MCF5206_MBUS_MBCR_TXAK    (0x08)
#define MCF5206_MBUS_MBCR_RSTA    (0x04)

#define MCF5206_MBUS_MBSR_MCF     (0x80)
#define MCF5206_MBUS_MBSR_MAAS    (0x40)
#define MCF5206_MBUS_MBSR_MBB     (0x20)
#define MCF5206_MBUS_MBSR_MAL     (0x10)
#define MCF5206_MBUS_MBSR_SRW     (0x04)
#define MCF5206_MBUS_MBSR_MIF     (0x02)
#define MCF5206_MBUS_MBSR_RXAK    (0x01)

/* ColdFire version independent versions */
#define MCF5XXX_MBUS_MADR_ADDR(a) MCF5206_MBUS_MADR_ADDR(a)

#define MCF5XXX_MBUS_MFDR_MBC(a)  MCF5206_MBUS_MFDR_MBC(a)

#define MCF5XXX_MBUS_MBCR_MEN     MCF5206_MBUS_MBCR_MEN 
#define MCF5XXX_MBUS_MBCR_MIEN    MCF5206_MBUS_MBCR_MIEN 
#define MCF5XXX_MBUS_MBCR_MSTA    MCF5206_MBUS_MBCR_MSTA 
#define MCF5XXX_MBUS_MBCR_MTX     MCF5206_MBUS_MBCR_MTX 
#define MCF5XXX_MBUS_MBCR_TXAK    MCF5206_MBUS_MBCR_TXAK 
#define MCF5XXX_MBUS_MBCR_RSTA    MCF5206_MBUS_MBCR_RSTA 

#define MCF5XXX_MBUS_MBSR_MCF     MCF5206_MBUS_MBSR_MCF  
#define MCF5XXX_MBUS_MBSR_MAAS    MCF5206_MBUS_MBSR_MAAS  
#define MCF5XXX_MBUS_MBSR_MBB     MCF5206_MBUS_MBSR_MBB 
#define MCF5XXX_MBUS_MBSR_MAL     MCF5206_MBUS_MBSR_MAL  
#define MCF5XXX_MBUS_MBSR_SRW     MCF5206_MBUS_MBSR_SRW
#define MCF5XXX_MBUS_MBSR_MIF     MCF5206_MBUS_MBSR_MIF
#define MCF5XXX_MBUS_MBSR_RXAK    MCF5206_MBUS_MBSR_RXAK


typedef struct
{
  unsigned8 madr;         /* M-BUS Address Register, 8-bit, R/W (00) */
  unsigned8 pack01[3];    /* 01-03 */
  unsigned8 mfdr;         /* M-BUS Frequency Divider Register, 8-bit, R/W (04) */
  unsigned8 pack02[3];    /* 05-07 */
  unsigned8 mbcr;         /* M-BUS Control Register, 8-bit, R/W (08) */
  unsigned8 pack03[3];    /* 09-0B */
  unsigned8 mbsr;         /* M-BUS Status Register, 8-bit, R/W (0C) */
  unsigned8 pack04[3];    /* 0D-0F */
  unsigned8 mbdr;         /* M-BUS Data I/O Register, 8-bit, R/W (10) */
  unsigned8 pack05[3];    /* 11-13 */
} mbusstruct;


#ifdef MCF5206E

/* DMA Channel */
#define MCF5206E_DMA_DCR_INT         (0x8000) /* Interrupt on Completion */
#define MCF5206E_DMA_DCR_EEXT        (0x4000) /* Enable External Request */
#define MCF5206E_DMA_DCR_CS          (0x2000) /* Cycle Steal     */
#define MCF5206E_DMA_DCR_AA          (0x1000) /* Auto Align      */
#define MCF5206E_DMA_DCR_BWC_DMA     (0x0000) /* Bandwidth: DMA Priority */
#define MCF5206E_DMA_DCR_BWC_512     (0x0200) /* Bandwidth:   512 Bytes  */
#define MCF5206E_DMA_DCR_BWC_1024    (0x0400) /* Bandwidth:  1024 Bytes  */
#define MCF5206E_DMA_DCR_BWC_2048    (0x0600) /* Bandwidth:  2048 Bytes  */
#define MCF5206E_DMA_DCR_BWC_4096    (0x0800) /* Bandwidth:  4096 Bytes  */
#define MCF5206E_DMA_DCR_BWC_8192    (0x0a00) /* Bandwidth:  8192 Bytes  */
#define MCF5206E_DMA_DCR_BWC_16384   (0x0c00) /* Bandwidth: 16384 Bytes  */
#define MCF5206E_DMA_DCR_BWC_32768   (0x0e00) /* Bandwidth: 32768 Bytes  */
#define MCF5206E_DMA_DCR_SAA         (0x0100) /* Single Address Access */
#define MCF5206E_DMA_DCR_SRW         (0x0080) /* Forces MRW Signal High  */
#define MCF5206E_DMA_DCR_SINC        (0x0040) /* Source Increment    */
#define MCF5206E_DMA_DCR_SSIZE_LONG  (0x0000) /* Source Size:  Longword  */
#define MCF5206E_DMA_DCR_SSIZE_BYTE  (0x0010) /* Source Size:  Byte    */
#define MCF5206E_DMA_DCR_SSIZE_WORD  (0x0020) /* Source Size:  Word    */
#define MCF5206E_DMA_DCR_SSIZE_LINE  (0x0030) /* Source Size:  Line    */
#define MCF5206E_DMA_DCR_DINC        (0x0008) /* Destination Increment */
#define MCF5206E_DMA_DCR_DSIZE_LONG  (0x0000) /* Destination Size:  Longword */
#define MCF5206E_DMA_DCR_DSIZE_BYTE  (0x0002) /* Destination Size:  Byte */
#define MCF5206E_DMA_DCR_DSIZE_WORD  (0x0004) /* Destination Size:  Word */
#define MCF5206E_DMA_DCR_START       (0x0001) /* Start Transfer    */

#define MCF5206E_DMA_DSR_CE          (0x40)  /* Configuration Error    */
#define MCF5206E_DMA_DSR_BES         (0x20)  /* Bus Error on Source    */
#define MCF5206E_DMA_DSR_BED         (0x10)  /* Bus Error on Destination */
#define MCF5206E_DMA_DSR_REQ         (0x04)  /* Request      */
#define MCF5206E_DMA_DSR_BSY         (0x02)  /* Busy       */
#define MCF5206E_DMA_DSR_DONE        (0x01)  /* Transaction Done   */


/* ColdFire version independent versions */
#define MCF5XXX_DMA_DCR_INT         MCF5206E_DMA_DCR_INT 
#define MCF5XXX_DMA_DCR_EEXT        MCF5206E_DMA_DCR_EEXT  
#define MCF5XXX_DMA_DCR_CS          MCF5206E_DMA_DCR_CS    
#define MCF5XXX_DMA_DCR_AA          MCF5206E_DMA_DCR_AA  
#define MCF5XXX_DMA_DCR_BWC_DMA     MCF5206E_DMA_DCR_BWC_DMA   
#define MCF5XXX_DMA_DCR_BWC_512     MCF5206E_DMA_DCR_BWC_512 
#define MCF5XXX_DMA_DCR_BWC_1024    MCF5206E_DMA_DCR_BWC_1024
#define MCF5XXX_DMA_DCR_BWC_2048    MCF5206E_DMA_DCR_BWC_2048 
#define MCF5XXX_DMA_DCR_BWC_4096    MCF5206E_DMA_DCR_BWC_4096  
#define MCF5XXX_DMA_DCR_BWC_8192    MCF5206E_DMA_DCR_BWC_8192   
#define MCF5XXX_DMA_DCR_BWC_16384   MCF5206E_DMA_DCR_BWC_16384 
#define MCF5XXX_DMA_DCR_BWC_32768   MCF5206E_DMA_DCR_BWC_32768  
#define MCF5XXX_DMA_DCR_SAA         MCF5206E_DMA_DCR_SAA 
#define MCF5XXX_DMA_DCR_SRW         MCF5206E_DMA_DCR_SRW    
#define MCF5XXX_DMA_DCR_SINC        MCF5206E_DMA_DCR_SINC   
#define MCF5XXX_DMA_DCR_SSIZE_LONG  MCF5206E_DMA_DCR_SSIZE_LONG
#define MCF5XXX_DMA_DCR_SSIZE_BYTE  MCF5206E_DMA_DCR_SSIZE_BYTE 
#define MCF5XXX_DMA_DCR_SSIZE_WORD  MCF5206E_DMA_DCR_SSIZE_WORD
#define MCF5XXX_DMA_DCR_SSIZE_LINE  MCF5206E_DMA_DCR_SSIZE_LINE
#define MCF5XXX_DMA_DCR_DINC        MCF5206E_DMA_DCR_DINC
#define MCF5XXX_DMA_DCR_DSIZE_LONG  MCF5206E_DMA_DCR_DSIZE_LONG 
#define MCF5XXX_DMA_DCR_DSIZE_BYTE  MCF5206E_DMA_DCR_DSIZE_BYTE 
#define MCF5XXX_DMA_DCR_DSIZE_WORD  MCF5206E_DMA_DCR_DSIZE_WORD
#define MCF5XXX_DMA_DCR_START       MCF5206E_DMA_DCR_START

#define MCF5XXX_DMA_DSR_CE          MCF5206E_DMA_DSR_CE
#define MCF5XXX_DMA_DSR_BES         MCF5206E_DMA_DSR_BES
#define MCF5XXX_DMA_DSR_BED         MCF5206E_DMA_DSR_BED
#define MCF5XXX_DMA_DSR_REQ         MCF5206E_DMA_DSR_REQ 
#define MCF5XXX_DMA_DSR_BSY         MCF5206E_DMA_DSR_BSY  
#define MCF5XXX_DMA_DSR_DONE        MCF5206E_DMA_DSR_DONE  

typedef struct
{
  unsigned32 sar;         /* DMA Source Address Register, 32-bit, R/W (00-03) */
  unsigned32 dar;         /* DMA Destination Address Register, 32-bit, R/W (04-07) */
  unsigned16 dcr;         /* DMA Control Register, 16-bit, R/W (08-09) */
  unsigned8  pack01[2];   /* 0A-0B */
  unsigned16 bcr;         /* DMA Byte Count Regsiter, 16-bit, R/W (0C-0D) */
  unsigned8  pack02[2];   /* 0E-0F */
  unsigned8  dsr;         /* DMA Status Register, 8-bit, R/W (10) */
  unsigned8  pack03[3];   /* 11-13 */
  unsigned8  divr;        /* DMA Interrupt Vector Register, 8-bit, R/W (14) */
  unsigned8  pack04[0x2B];/* 15-3F */
} dmastruct;

#endif


/* System Integration Module */
 
#define MCF5206_SIM_SIMR_FRZ1   (0x80)
#define MCF5206_SIM_SIMR_FRZ0   (0x40)
#define MCF5206_SIM_SIMR_BL     (0x01)

#define MCF5206_SIM_ICR_AVEC    (0x80)
#define MCF5206_SIM_ICR_IL(a)   (((a)&0x07)<<2)
#define MCF5206_SIM_ICR_IP(a)   (((a)&0x03))

#define MCF5206E_SIM_IMR_DMA1   (0x8000)
#define MCF5206E_SIM_IMR_DMA0   (0x4000)
#define MCF5206_SIM_IMR_UART2   (0x2000)
#define MCF5206_SIM_IMR_UART1   (0x1000)
#define MCF5206_SIM_IMR_MBUS    (0x0800)
#define MCF5206_SIM_IMR_T2      (0x0400)
#define MCF5206_SIM_IMR_T1      (0x0200)
#define MCF5206_SIM_IMR_SWT     (0x0100)
#define MCF5206_SIM_IMR_EINT7   (0x0080)
#define MCF5206_SIM_IMR_EINT6   (0x0040)
#define MCF5206_SIM_IMR_EINT5   (0x0020)
#define MCF5206_SIM_IMR_EINT4   (0x0010)
#define MCF5206_SIM_IMR_EINT3   (0x0008)
#define MCF5206_SIM_IMR_EINT2   (0x0004)
#define MCF5206_SIM_IMR_EINT1   (0x0002)

#define MCF5206E_SIM_IPR_DMA1   (0x8000)
#define MCF5206E_SIM_IPR_DMA0   (0x4000)
#define MCF5206_SIM_IPR_UART2   (0x2000)
#define MCF5206_SIM_IPR_UART1   (0x1000)
#define MCF5206_SIM_IPR_MBUS    (0x0800)
#define MCF5206_SIM_IPR_T2      (0x0400)
#define MCF5206_SIM_IPR_T1      (0x0200)
#define MCF5206_SIM_IPR_SWT     (0x0100)
#define MCF5206_SIM_IPR_EINT7   (0x0080)
#define MCF5206_SIM_IPR_EINT6   (0x0040)
#define MCF5206_SIM_IPR_EINT5   (0x0020)
#define MCF5206_SIM_IPR_EINT4   (0x0010)
#define MCF5206_SIM_IPR_EINT3   (0x0008)
#define MCF5206_SIM_IPR_EINT2   (0x0004)
#define MCF5206_SIM_IPR_EINT1   (0x0002)

#define MCF5206_SIM_RSR_HRST    (0x80)
#define MCF5206_SIM_RSR_SWTR    (0x20)

#define MCF5206_SIM_SYPCR_SWE       (0x80)
#define MCF5206_SIM_SYPCR_SWRI      (0x40)
#define MCF5206_SIM_SYPCR_SWT_2_9   (0x00)
#define MCF5206_SIM_SYPCR_SWT_2_11  (0x08)
#define MCF5206_SIM_SYPCR_SWT_2_13  (0x10)
#define MCF5206_SIM_SYPCR_SWT_2_15  (0x18)
#define MCF5206_SIM_SYPCR_SWT_2_18  (0x20)
#define MCF5206_SIM_SYPCR_SWT_2_20  (0x28)
#define MCF5206_SIM_SYPCR_SWT_2_22  (0x30)
#define MCF5206_SIM_SYPCR_SWT_2_24  (0x38)
#define MCF5206_SIM_SYPCR_BME       (0x04)
#define MCF5206_SIM_SYPCR_BM_1024   (0x00)
#define MCF5206_SIM_SYPCR_BM_512    (0x01)
#define MCF5206_SIM_SYPCR_BM_256    (0x02)
#define MCF5206_SIM_SYPCR_BM_128    (0x03)

#define MCF5206_SIM_SWIVR_SWIV(a)   ((a)&0x00FF)

#define MCF5206E_SIM_PAR_PAR9       (0x0200)
#define MCF5206E_SIM_PAR_PAR8_DMA1  (0x0200)
#define MCF5206E_SIM_PAR_PAR8_TIN1  (0x0000)
#define MCF5206E_SIM_PAR_PAR8_DMA0  (0x0100)
#define MCF5206E_SIM_PAR_PAR8_TIN0  (0x0000)
#define MCF5206E_SIM_PAR_PAR8       (0x0100)

#define MCF5206_SIM_PAR_PAR7        (0x80)
#define MCF5206_SIM_PAR_PAR7_RSTO   (0x00)
#define MCF5206_SIM_PAR_PAR7_RTS2   (0x80)
#define MCF5206_SIM_PAR_PAR6        (0x40)
#define MCF5206_SIM_PAR_PAR6_IRQ    (0x00)
#define MCF5206_SIM_PAR_PAR6_IPL    (0x40)
#define MCF5206_SIM_PAR_PAR5        (0x20)
#define MCF5206_SIM_PAR_PAR5_PP74   (0x00)
#define MCF5206_SIM_PAR_PAR5_PST    (0x20)
#define MCF5206_SIM_PAR_PAR4        (0x10)
#define MCF5206_SIM_PAR_PAR4_PP30   (0x00)
#define MCF5206_SIM_PAR_PAR4_DDATA  (0x10)
#define MCF5206_SIM_PAR_PAR3        (0x08)
#define MCF5206_SIM_PAR_PAR2        (0x04)
#define MCF5206_SIM_PAR_PAR1        (0x02)
#define MCF5206_SIM_PAR_PAR0        (0x01)

#define MCF5206_PP_PPDDR_DDR7_INPUT   (~0x80)
#define MCF5206_PP_PPDDR_DDR7_OUTPUT  ( 0x80)
#define MCF5206_PP_PPDDR_DDR6_INPUT   (~0x40)
#define MCF5206_PP_PPDDR_DDR6_OUTPUT  ( 0x40)
#define MCF5206_PP_PPDDR_DDR5_INPUT   (~0x20)
#define MCF5206_PP_PPDDR_DDR5_OUTPUT  ( 0x20)
#define MCF5206_PP_PPDDR_DDR4_INPUT   (~0x10)
#define MCF5206_PP_PPDDR_DDR4_OUTPUT  ( 0x10)
#define MCF5206_PP_PPDDR_DDR3_INPUT   (~0x08)
#define MCF5206_PP_PPDDR_DDR3_OUTPUT  ( 0x08)
#define MCF5206_PP_PPDDR_DDR2_INPUT   (~0x04)
#define MCF5206_PP_PPDDR_DDR2_OUTPUT  ( 0x04)
#define MCF5206_PP_PPDDR_DDR1_INPUT   (~0x02)
#define MCF5206_PP_PPDDR_DDR1_OUTPUT  ( 0x02)
#define MCF5206_PP_PPDDR_DDR0_INPUT   (~0x01)
#define MCF5206_PP_PPDDR_DDR0_OUTPUT  ( 0x01)

#define MCF5206_PP_PPDAT_DAT7   ( 0x80)
#define MCF5206_PP_PPDAT_DAT6   ( 0x40)
#define MCF5206_PP_PPDAT_DAT5   ( 0x20)
#define MCF5206_PP_PPDAT_DAT4   ( 0x10)
#define MCF5206_PP_PPDAT_DAT3   ( 0x08)
#define MCF5206_PP_PPDAT_DAT2   ( 0x04)
#define MCF5206_PP_PPDAT_DAT1   ( 0x02)
#define MCF5206_PP_PPDAT_DAT0   ( 0x01)


#define MCF5206_CS_CSAR_BASE(a)   (((a)&0xFFFF0000)>>16)

#define MCF5206_CS_CSMR_MASK_32M    (0x01FF0000)
#define MCF5206_CS_CSMR_MASK_16M    (0x00FF0000)
#define MCF5206_CS_CSMR_MASK_8M     (0x007F0000)
#define MCF5206_CS_CSMR_MASK_4M     (0x003F0000)
#define MCF5206_CS_CSMR_MASK_2M     (0x001F0000)
#define MCF5206_CS_CSMR_MASK_1M     (0x000F0000)
#define MCF5206_CS_CSMR_MASK_1024K  (0x000F0000)
#define MCF5206_CS_CSMR_MASK_512K   (0x00070000)
#define MCF5206_CS_CSMR_MASK_256K   (0x00030000)
#define MCF5206_CS_CSMR_MASK_128K   (0x00010000)
#define MCF5206_CS_CSMR_MASK_64K    (0x00000000)
#define MCF5206_CS_CSMR_SC          (0x00000010)
#define MCF5206_CS_CSMR_SD          (0x00000008)
#define MCF5206_CS_CSMR_UC          (0x00000004)
#define MCF5206_CS_CSMR_UD          (0x00000002)
#define MCF5206_CS_CSMR1_CPU        (0x00000020)

#define MCF5206_CS_CSCR_WS_MASK     (0x3C00)
#define MCF5206_CS_CSCR_WS(a)       (((a)&0x0F)<<10)
#define MCF5206_CS_CSCR_BRST        (0x0200)
#define MCF5206_CS_CSCR_AA          (0x0100)
#define MCF5206_CS_CSCR_PS_8        (0x0040)
#define MCF5206_CS_CSCR_PS_16       (0x0080)
#define MCF5206_CS_CSCR_PS_32       (0x0000)
#define MCF5206_CS_CSCR_EMAA        (0x0020)
#define MCF5206_CS_CSCR_ASET        (0x0010)
#define MCF5206_CS_CSCR_WRAH        (0x0008)
#define MCF5206_CS_CSCR_RDAH        (0x0004)
#define MCF5206_CS_CSCR_WR          (0x0002)
#define MCF5206_CS_CSCR_RD          (0x0001)

#define MCF5206_CS_DMCR_WS_MASK     (0x3C00)
#define MCF5206_CS_DMCR_WS(a)       (((a)&0x0F)<<10)
#define MCF5206_CS_DMCR_BRST        (0x0200)
#define MCF5206_CS_DMCR_AA          (0x0100)
#define MCF5206_CS_DMCR_PS_8        (0x0040)
#define MCF5206_CS_DMCR_PS_16       (0x0080)
#define MCF5206_CS_DMCR_PS_32       (0x0000)
#define MCF5206_CS_DMCR_EMAA        (0x0020)
#define MCF5206_CS_DMCR_WRAH        (0x0008)
#define MCF5206_CS_DMCR_RDAH        (0x0004)

#define MCF5206_IACK_ADDRESS  (MCF5206_CS_CSAR_BASE(0xFFFFFFE0))
#define MCF5206_IACK_MASK     (MCF5206_CS_CSMR_MASK_64K)


#define MCF5206_DRAMC_DCRR_RC(a)  ((a)&0x0FFF)

#define MCF5206_DRAMC_DCTR_DAEM   (0x8000)
#define MCF5206_DRAMC_DCTR_EDO    (0x4000)
#define MCF5206_DRAMC_DCTR_RCD    (0x1000)
#define MCF5206_DRAMC_DCTR_RSH_1  (0x0000)
#define MCF5206_DRAMC_DCTR_RSH_2  (0x0200)
#define MCF5206_DRAMC_DCTR_RSH_3  (0x0400)
#define MCF5206_DRAMC_DCTR_CRP_15 (0x0000)
#define MCF5206_DRAMC_DCTR_CRP_25 (0x0020)
#define MCF5206_DRAMC_DCTR_CRP_35 (0x0040)
#define MCF5206_DRAMC_DCTR_CAS    (0x0008)
#define MCF5206_DRAMC_DCTR_CP     (0x0002)
#define MCF5206_DRAMC_DCTR_CSR    (0x0001)

#define MCF5206_DRAMC_DCAR_BASE(a)  (((a)&0xFFFE0000)>>16)

#define MCF5206_DRAMC_DCMR_MASK_128M  (0x07FE0000)
#define MCF5206_DRAMC_DCMR_MASK_64M   (0x03FE0000)
#define MCF5206_DRAMC_DCMR_MASK_32M   (0x01FE0000)
#define MCF5206_DRAMC_DCMR_MASK_16M   (0x00FE0000)
#define MCF5206_DRAMC_DCMR_MASK_8M    (0x007E0000)
#define MCF5206_DRAMC_DCMR_MASK_4M    (0x003E0000)
#define MCF5206_DRAMC_DCMR_MASK_2M    (0x001E0000)
#define MCF5206_DRAMC_DCMR_MASK_1M    (0x000E0000)
#define MCF5206_DRAMC_DCMR_MASK_1024K (0x00060000)
#define MCF5206_DRAMC_DCMR_MASK_256K  (0x00020000)
#define MCF5206_DRAMC_DCMR_MASK_128K  (0x00000000)
#define MCF5206_DRAMC_DCMR_SC         (0x00000010)
#define MCF5206_DRAMC_DCMR_SD         (0x00000008)
#define MCF5206_DRAMC_DCMR_UC         (0x00000004)
#define MCF5206_DRAMC_DCMR_UD         (0x00000002)

#define MCF5206_DRAMC_DCCR_PS_32        (0x00)
#define MCF5206_DRAMC_DCCR_PS_16        (0xC0)
#define MCF5206_DRAMC_DCCR_PS_8         (0x40)
#define MCF5206_DRAMC_DCCR_PS_MASK      (0xC0)
#define MCF5206_DRAMC_DCCR_BPS_512B     (0x00)
#define MCF5206_DRAMC_DCCR_BPS_1K       (0x10)
#define MCF5206_DRAMC_DCCR_BPS_2K       (0x20)
#define MCF5206_DRAMC_DCCR_PM_NORMAL    (0x00)
#define MCF5206_DRAMC_DCCR_PM_BURSTPAGE (0x04)
#define MCF5206_DRAMC_DCCR_PM_FASTPAGE  (0x0C)
#define MCF5206_DRAMC_DCCR_WR           (0x02)
#define MCF5206_DRAMC_DCCR_RD           (0x01)


typedef struct
{
  unsigned8  pack01[3];   /* 000-002 */
  unsigned8  simr;        /* SIM Configuration Register, 8-bit, R/W (003) */
  unsigned8  pack02[0x10];/* 004-013 */
  unsigned8  icr1;        /* Interrupt Control Register Ext1, 8-bit, R/W (014) */
  unsigned8  icr2;        /* Interrupt Control Register Ext2, 8-bit, R/W (015) */
  unsigned8  icr3;        /* Interrupt Control Register Ext3, 8-bit, R/W (016) */
  unsigned8  icr4;        /* Interrupt Control Register Ext4, 8-bit, R/W (017) */
  unsigned8  icr5;        /* Interrupt Control Register Ext5, 8-bit, R/W (018) */
  unsigned8  icr6;        /* Interrupt Control Register Ext6, 8-bit, R/W (019) */
  unsigned8  icr7;        /* Interrupt Control Register Ext7, 8-bit, R/W (01A) */
  unsigned8  icr8;        /* Interrupt Control Register Ext8, 8-bit, R/W (01B) */
  unsigned8  icr9;        /* Interrupt Control Register Ext9, 8-bit, R/W (01C) */
  unsigned8  icr10;       /* Interrupt Control Register Ext10, 8-bit, R/W (01D) */
  unsigned8  icr11;       /* Interrupt Control Register Ext11, 8-bit, R/W (01E) */
  unsigned8  icr12;       /* Interrupt Control Register Ext12, 8-bit, R/W (01F) */
  unsigned8  icr13;       /* Interrupt Control Register Ext13, 8-bit, R/W (020) */
#ifdef MCF5206E
  unsigned8  icr14;       /* Interrupt Control Register Ext14, 8-bit, R/W (021) */
  unsigned8  icr15;       /* Interrupt Control Register Ext15, 8-bit, R/W (022) */
#else
  unsigned8  pack03a[0x2];/* 021-022 */
#endif
  unsigned8  pack03b[0x13]; /* 023-035 */
  unsigned16 imr;         /* Interrupt Mask Register, 16-bit, R/W (036-037) */
  unsigned8  pack3a[2];   /* 038-039 */
  unsigned16 ipr;         /* Interrupt Pending Register, 16-bit, R (03A-3B) */
  unsigned8  pack04[4];   /* 03C-03F */
  unsigned8  rsr;         /* Reset Status Register, 8-bit, R/W (040) */
  unsigned8  sypcr;       /* System Protection Control Register, 8-bit, R/W (041) */
  unsigned8  swivr;       /* Software Watchdog Interrupt Vector Register, 8-bit, W (042) */
  unsigned8  swsr;        /* Software Watchdog Service Register, 8-bit, W (043) */
  unsigned8  pack05[2];   /* 044-045 */


/** DRAM Controller Registers **/
  
  unsigned16 dcrr;        /* DRAM Controller Refresh Register, 16-bit, R/W (046-047) */
  unsigned8  pack06[2];   /* 048-049 */
  unsigned16 dctr;        /* DRAM Controller Timing Register, 16-bit, R/W (04A-04B) */

  unsigned16 dcar0;       /* DRAM Controller Bank 0 Address Register, 16-bit, R/W (04C-04D) */
  unsigned8  pack07[2];   /* 04E-04F */
  unsigned32 dcmr0;       /* DRAM Controller Bank 0 Mask Register, 32-bit, R/W (050-053) */
  unsigned8  pack08[3];   /* 054-056 */
  unsigned8  dccr0;       /* DRAM Controller Bank 0 Control Register, 8-bit, R/W (057) */

  unsigned16 dcar1;       /* DRAM Controller Bank 1 Address Register, 16-bit, R/W (058-059) */
  unsigned8  pack09[2];   /* 05A-05B */
  unsigned32 dcmr1;       /* DRAM Controller Bank 1 Mask Register, 32-bit, R/W (05C-05F) */
  unsigned8  pack10[3];   /* 060-062 */
  unsigned8  dccr1;       /* DRAM Controller Bank 1 Control Register, 8-bit, R/W (063) */
  

/** Chip Select Registers **/
  
  csstruct   cs[8];       /* Chip-Select registers (064-0C3) */
  unsigned8  pack11[2];   /* 0C4-0C5 */
  unsigned16 dmcr;        /* Default Memory Control Register, 16-bit, R/W (0C6-0C7) */
  unsigned8  pack12[2];   /* 0C8-0C9 */


/** General Purpose I/O **/
#ifdef MCF5206E
  unsigned16 par;         /* Pin Assignment Register, 8-bit, R/W (0CA-0CB) */
#else
  unsigned8 pack12a;      /* 0CA */
  unsigned8 par;          /* Pin Assignment Register, 8-bit, R/W (0CB) */
#endif
  unsigned8 pack13[0x34]; /* 0CC-0FF */
  tmrstruct timer1;       /* Timer 1 Module (100-111) */
  unsigned8 pack14[0xE];  /* 112-11F */
  tmrstruct timer2;       /* Timer 2 Module (120-131) */
  unsigned8 pack15[0xE];  /* 132-13F */
  uartstruct uart1;       /* UART 1 Module (140-17F) */
  uartstruct uart2;       /* UART 2 Module (180-1BF) */
  unsigned8 pack18[5];    /* 1C0-1C4 */
  unsigned8 ppddr;        /* Port A Data Direction Register, 8-bit, R/W (1C5) */
  unsigned8 pack19[3];    /* 1C6-1C8 */
  unsigned8 ppdat;        /* Port A Data Direction Register, 8-bit, R/W (1C9) */
  unsigned8 pack20[0x16]; /* 1CA-1DF */
  mbusstruct      mbus;   /* MBUS Module (1E0-1F3) */
#ifdef MCF5206E
  unsigned8 pack21[0xC];  /* 1F4-1FF */
  dmastruct dma[2];       /* 2 DMA Channels (200 - 27F) */
#endif

} SIM5206;


#endif /* __MCF5206_H */
