/******************************************************/
/**  Dummy Time() procedure so that Dhrystone works  **/
/**  This only works if program run time is < 65 sec **/
/******************************************************/
#ifdef MCF5307
  #include "sim5307.h"

  static volatile SIM5307 *sim = (SIM5307 *)0x10000000;
#else
  #include "sim5206.h"

  static volatile SIM5206 *sim = (SIM5206 *)0x10000000;
#endif

#define asm __asm__
#define volatile __volatile__


#define m68k_set_cacr( _cacr ) \
  asm volatile ( "movec %0,%%cacr\n\t" \
                 "nop\n" \
                 : : "d" (_cacr) )

#define m68k_set_acr0( _acr0 ) \
  asm volatile (  "movec %0,%%acr0\n\t" \
                  "nop\n\t" \
                  : : "d" (_acr0) )

#define m68k_set_acr1( _acr1 ) \
  asm volatile (  "movec %0,%%acr1\n\t" \
                  "nop\n\t" \
                  : : "d" (_acr1) )



long time()
{
#if defined(VARIANT_sbc5307)
  return (sim->timer1.tcn * 1000) / 11250; /* 45MHz bus speed */
#elif defined(VARIANT_sbc5206e) || defined(VARIANT_sbc5206elite)
  return (sim->timer1.tcn * 1000) / 13500; /* 54MHz bus speed */
#elif defined(VARIANT_sbc5206)
  return (sim->timer1.tcn * 1000) / 6250; /* 25MHz bus speed */
#else
  #error "Undefined clock speed variant!"
#endif
}


void Init_Timer( void )
{
  /* Enable the ColdFire cache */
  /* We make all FLASH and DRAM accesses cached */

#if defined(VARIANT_sbc5307)
  m68k_set_acr0( 0
                 | MCF5307_ACR_BASE(0x00000000) 	
                 | MCF5307_ACR_MASK(0x00000000)	
                 | MCF5307_ACR_E		
                 | MCF5307_ACR_S_IGNORE		
                 | MCF5307_ACR_CM_00);

  m68k_set_acr1( 0
                 | MCF5307_ACR_BASE(0xFFE00000) 	
                 | MCF5307_ACR_MASK(0x00000000)	
                 | MCF5307_ACR_E		
                 | MCF5307_ACR_S_IGNORE		
                 | MCF5307_ACR_CM_00);

  m68k_set_cacr( MCF5307_CACR_EC     |
                 MCF5307_CACR_DCM_11 |
                 MCF5307_CACR_CINVA  );

#elif defined(VARIANT_sbc5206e) || defined(VARIANT_sbc5206elite) || defined(VARIANT_sbc5206)
  m68k_set_cacr( MCF5206_CACR_CENB |
                 MCF5206_CACR_DBWE |
                 MCF5206_CACR_CINV  );

#else
  #error "Undefined cache variant!"
#endif

  /* Reset timer1 */
  sim->timer1.tmr = MCF5XXX_TIMER_TMR_RST;    
  sim->timer1.tmr = MCF5XXX_TIMER_TMR_CLK_STOP;   
  sim->timer1.tmr = MCF5XXX_TIMER_TMR_RST;    
  sim->timer1.tcn = 0; /* zero count */
  sim->timer1.ter = MCF5XXX_TIMER_TER_REF | MCF5XXX_TIMER_TER_CAP; /* clear pending */

  /* Setup Timer */
  sim->timer1.tmr = MCF5XXX_TIMER_TMR_PS( 250 )  |
                    MCF5XXX_TIMER_TMR_CE_NONE    |
                    MCF5XXX_TIMER_TMR_FRR        |
                    MCF5XXX_TIMER_TMR_CLK_DIV16  |
                    MCF5XXX_TIMER_TMR_RST;
}




