/*
 *  Motorola MCF5307 ColdFire System Integration Module Header
 *
 *  Header file for the Motorola ColdFire MCF5307 internal modules.
 *  This contains a structure which can be used to access internal
 *  MCF5307 modules easily as well as bit pattern definitions for
 *  most registers.
 *
 *  This file was compiled from MCF5307UM/AD, Motorola assembler 
 *  header file and SBC5307 eval board monitor source.
 *
 *  Author:
 *    David Fiddes, D.J@fiddes.net
 *    http://fiddes.net/coldfire/
 *
 *  This code has no copyright and may freely be used in whatever 
 *  manner you see fit.
 *
 *  THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY 
 *  OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT    
 *  LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR    
 *  FITNESS FOR A PARTICULAR PURPOSE.                              
 */
#ifndef __MCF5307_H
#define __MCF5307_H

/*
 * Cache and Access Control Register routines and defintions
 */

#define MCF5307_CACR_EC       (0x80000000)  /* Cache Enable               */
#define MCF5307_CACR_ESB      (0x20000000)  /* Enable Store Buffer        */
#define MCF5307_CACR_DPI      (0x10000000)  /* Disable CPUSHL Invalidation*/
#define MCF5307_CACR_HLCK     (0x08000000)  /* 1/2 Cache Lock Mode        */
#define MCF5307_CACR_CINVA    (0x01000000)  /* Cache Invalidate All       */
#define MCF5307_CACR_DNFB     (0x00000400)  /* Default Noncacheable Fill Buffer */
#define MCF5307_CACR_DCM_00   (0x00000000)  /* Cacheable, writethrough    */
#define MCF5307_CACR_DCM_01   (0x00000100)  /* Cacheable, copyback        */
#define MCF5307_CACR_DCM_10   (0x00000200)  /* Cache-Inhibited, precise   */
#define MCF5307_CACR_DCM_11   (0x00000300)  /* Cache-Inhibited, imprecise */
#define MCF5307_CACR_DW       (0x00000020)  /* Default Write Protect      */

#define MCF5307_ACR_BASE(a)   ((a)&0xFF000000)  /* Address Base       */
#define MCF5307_ACR_MASK(a)   (((a)&0xFF000000)>>8) /* Address Mask       */
#define MCF5307_ACR_E         (0x00008000)  /* Enable         */
#define MCF5307_ACR_S_USER    (0x00000000)  /* User Mode Access       */
#define MCF5307_ACR_S_SUPER   (0x00002000)  /* Supervisor Mode Access     */
#define MCF5307_ACR_S_IGNORE  (0x00004000)  /* Ignore Mode Access       */
#define MCF5307_ACR_CM_00     (0x00000000)  /* Cacheable, writethrough      */
#define MCF5307_ACR_CM_01     (0x00000020)  /* Cacheable, copyback        */
#define MCF5307_ACR_CM_10     (0x00000040)  /* Cache-Inhibited, precise     */
#define MCF5307_ACR_CM_11     (0x00000060)  /* Cache-Inhibited, imprecise     */
#define MCF5307_ACR_WP        (0x00000004)  /* Write Protect        */

#define MCF5307_VBR_BASE(a)   ((a)&0xFFF00000)  /* Vector Base Address      */

#define MCF5307_RAMBAR_BASE(a)  ((a)&0xFFFFFE00)  /* Base Address       */
#define MCF5307_RAMBAR_WP     (0x00000100)  /* Write Protect        */
#define MCF5307_RAMBAR_AS_CPU (0x00000020)  /* CPU Space/Interrupt acknowledge  */
#define MCF5307_RAMBAR_AS_SC  (0x00000010)  /* Supervisor Code        */
#define MCF5307_RAMBAR_AS_SD  (0x00000008)  /* Supervisor Data        */
#define MCF5307_RAMBAR_AS_UC  (0x00000004)  /* User Code          */
#define MCF5307_RAMBAR_AS_UD  (0x00000002)  /* User Data          */
#define MCF5307_RAMBAR_V      (0x00000001)  /* Valid          */

#define MCF5307_MBAR_BASE(a)  ((a)&0xFFFFFC00)  /* Base Address       */
#define MCF5307_MBAR_WP       (0x00000200)  /* Write Protect        */
#define MCF5307_MBAR_SC       (0x00000010)  /* Mask Supervisor Code Space     */
#define MCF5307_MBAR_SD       (0x00000008)  /* Mask Supervisor Data Space     */
#define MCF5307_MBAR_UC       (0x00000004)  /* Mask User Code Space       */
#define MCF5307_MBAR_UD       (0x00000002)  /* Mask User Data Space       */
#define MCF5307_MBAR_V        (0x00000001)  /* Valid          */


/***********************************************************************/
/*                                                                     */
/*  These definitions only exists in the CSMR for Banks 0 and 1.       */
/*                                                                     */
/***********************************************************************/

#define MCF5307_CS_CSMR_MASK_4G     (0xFFFF0000)  /* Set Bank to 4G    */
#define MCF5307_CS_CSMR_MASK_2G     (0x7FFF0000)  /* Set Bank to 2G    */
#define MCF5307_CS_CSMR_MASK_1G     (0x3FFF0000)  /* Set Bank to 1G    */
#define MCF5307_CS_CSMR_MASK_1024M  (0x3FFF0000)  /* Set Bank to 1024M     */
#define MCF5307_CS_CSMR_MASK_512M   (0x1FFF0000)  /* Set Bank to 512M    */
#define MCF5307_CS_CSMR_MASK_256M   (0x0FFF0000)  /* Set Bank to 256M    */
#define MCF5307_CS_CSMR_MASK_128M   (0x07FF0000)  /* Set Bank to 128M    */
#define MCF5307_CS_CSMR_MASK_64M    (0x03FF0000)  /* Set Bank to 64M     */
#define MCF5307_CS_CSMR_MASK_32M    (0x01FF0000)  /* Set Bank to 32M     */
#define MCF5307_CS_CSMR_MASK_16M    (0x00FF0000)  /* Set Bank to 16M     */
#define MCF5307_CS_CSMR_MASK_8M     (0x007F0000)  /* Set Bank to 8M    */
#define MCF5307_CS_CSMR_MASK_4M     (0x003F0000)  /* Set Bank to 4M    */
#define MCF5307_CS_CSMR_MASK_2M     (0x001F0000)  /* Set Bank to 2M    */
#define MCF5307_CS_CSMR_MASK_1M     (0x000F0000)  /* Set Bank to 1M    */
#define MCF5307_CS_CSMR_MASK_1024K  (0x000F0000)  /* Set Bank to 1024K     */
#define MCF5307_CS_CSMR_MASK_512K   (0x00070000)  /* Set Bank to 512K    */
#define MCF5307_CS_CSMR_MASK_256K   (0x00030000)  /* Set Bank to 256K    */
#define MCF5307_CS_CSMR_MASK_128K   (0x00010000)  /* Set Bank to 128K    */
#define MCF5307_CS_CSMR_MASK_64K    (0x00000000)  /* Set Bank to 64K     */
#define MCF5307_CS_CSMR_CPU         (0x00000020)  /* CPU and IACK Cycle Mask */

/***********************************************************************/
/*                                                                     */
/*  The following definitions exist for all Banks 0-7                  */
/*                                                                     */
/***********************************************************************/

#define MCF5307_CS_CSAR(a)    (((a)&0xFFFF0000)>>16)  /* Base Address    */
#define MCF5307_CS_CSBAR(a)   (((a)&0xFF000000)>>24)  /* Base for CS2-7  */

#define MCF5307_CS_CSMR_WP    (0x00000100)  /* Write Protect     */
#define MCF5307_CS_CSMR_AM    (0x00000040)  /* Alternate Master Mask   */
#define MCF5307_CS_CSMR_SC    (0x00000010)  /* Supervisor Code Mask    */
#define MCF5307_CS_CSMR_SD    (0x00000008)  /* Supervisor Data Mask    */
#define MCF5307_CS_CSMR_UC    (0x00000004)  /* User Code Mask    */
#define MCF5307_CS_CSMR_UD    (0x00000002)  /* User Data Mask    */
#define MCF5307_CS_CSMR_V     (0x00000001)  /* Valid Register    */

#define MCF5307_CS_CSCR_WS(a) (((a)&0x0F)<<10) /* Wait States      */
#define MCF5307_CS_CSCR_AA    (0x0100)  /* Auto Acknowledge Enable */
#define MCF5307_CS_CSCR_PS_8  (0x0040)  /* Port Size:   8-bit    */
#define MCF5307_CS_CSCR_PS_16 (0x0080)  /* Port Size:  16-bit    */
#define MCF5307_CS_CSCR_PS_32 (0x0000)  /* Port Size:  32-bit    */
#define MCF5307_CS_CSCR_BEM   (0x0020)  /* Byte Module Enable    */
#define MCF5307_CS_CSCR_BSTR  (0x0010)  /* Burst Read Enable     */
#define MCF5307_CS_CSCR_BSTW  (0x0008)  /* Burst Write Enable    */

/* Absolute Chip Select structure (similar to other ColdFire family) */
typedef struct
{
  unsigned16 csar;        /* Chip-Select X Base Address Register, 16-bit, R/W (00-01) */
  unsigned8  pack01[2];   /* 02-03 */
  unsigned32 csmr;        /* Chip-Select X Address Mask Register, 32-bit, R/W (04-07) */
  unsigned8  pack02[2];   /* 08-09 */
  unsigned16 cscr;        /* Chip-Select X Control Register, 16-bit, R/W (0A-0B) */
} csstruct_abs;

/* Relative Chip Select structure - relative to csbar */
typedef struct
{
  unsigned32 csmr;        /* Chip-Select X Address Mask Register, 32-bit, R/W (00-03) */
  unsigned8  pack01[2];   /* 04-05 */
  unsigned16 cscr;        /* Chip-Select X Control Register, 16-bit, R/W (06-07) */
  unsigned8  pack02[4];   /* 08-0B */
} csstruct_rel;


#define MCF5307_TIMER_TMR_PS(a)     (((a)&0x00FF)<<8) /* Prescaler Value    */
#define MCF5307_TIMER_TMR_CE_ANY    (0x00C0) /* Capture on Any Edge     */
#define MCF5307_TIMER_TMR_CE_FALL   (0x0080) /* Capture on Falling Edge   */
#define MCF5307_TIMER_TMR_CE_RISE   (0x0040) /* Capture on Rising Edge    */
#define MCF5307_TIMER_TMR_CE_NONE   (0x0000) /* Disable Capture Event   */
#define MCF5307_TIMER_TMR_OM        (0x0020) /* Output Mode       */
#define MCF5307_TIMER_TMR_ORI       (0x0010) /* Output Reference Interrupt Enable */
#define MCF5307_TIMER_TMR_FRR       (0x0008) /* Restart After Reference Value */
#define MCF5307_TIMER_TMR_CLK_TIN   (0x0006) /* TIN is Input Clock Source   */
#define MCF5307_TIMER_TMR_CLK_DIV16 (0x0004) /* Sys Clk / 16 is Input Clock Source  */
#define MCF5307_TIMER_TMR_CLK_MSCLK (0x0002) /* Sys Clk is Input Clock Source */
#define MCF5307_TIMER_TMR_CLK_STOP  (0x0000) /* Stop Count        */
#define MCF5307_TIMER_TMR_RST       (0x0001) /* Enable Timer      */
                                             /* H to L will Reset Registers   */

#define MCF5307_TIMER_TER_REF       (0x02)  /* Output Reference Event   */
#define MCF5307_TIMER_TER_CAP       (0x01)  /* Capture Event      */

/* ColdFire version independent versions */
#define MCF5XXX_TIMER_TMR_PS(a)     MCF5307_TIMER_TMR_PS(a)
#define MCF5XXX_TIMER_TMR_CE_ANY    MCF5307_TIMER_TMR_CE_ANY
#define MCF5XXX_TIMER_TMR_CE_FALL   MCF5307_TIMER_TMR_CE_FALL
#define MCF5XXX_TIMER_TMR_CE_RISE   MCF5307_TIMER_TMR_CE_RISE
#define MCF5XXX_TIMER_TMR_CE_NONE   MCF5307_TIMER_TMR_CE_NONE
#define MCF5XXX_TIMER_TMR_OM        MCF5307_TIMER_TMR_OM
#define MCF5XXX_TIMER_TMR_ORI       MCF5307_TIMER_TMR_ORI   
#define MCF5XXX_TIMER_TMR_FRR       MCF5307_TIMER_TMR_FRR 
#define MCF5XXX_TIMER_TMR_CLK_TIN   MCF5307_TIMER_TMR_CLK_TIN
#define MCF5XXX_TIMER_TMR_CLK_DIV16 MCF5307_TIMER_TMR_CLK_DIV16
#define MCF5XXX_TIMER_TMR_CLK_MSCLK MCF5307_TIMER_TMR_CLK_MSCLK
#define MCF5XXX_TIMER_TMR_CLK_STOP  MCF5307_TIMER_TMR_CLK_STOP
#define MCF5XXX_TIMER_TMR_RST       MCF5307_TIMER_TMR_RST

#define MCF5XXX_TIMER_TER_REF       MCF5307_TIMER_TER_REF
#define MCF5XXX_TIMER_TER_CAP       MCF5307_TIMER_TER_CAP  

typedef struct
{
  unsigned16 tmr;         /* TIMERx Mode Register, 16-bit, R/W (00-01) */
  unsigned8  pack01[2];   /* 02-03 */
  unsigned16 trr;         /* TIMERx Mode Register, 16-bit, R/W (04-05) */
  unsigned8  pack02[2];   /* 06-07 */
  unsigned16 tcr;         /* TIMERx Capture Register, 16-bit, R (08-09) */
  unsigned8  pack03[2];   /* 0A-0B */
  unsigned16 tcn;         /* TIMERx Counter, 16-bit, R/W (0C-0D) */
  unsigned8  pack04[3];   /* 0E-10 */
  unsigned8  ter;         /* TIMERx Event Register, 8-bit, R/W (11) */
} tmrstruct;
  

/***********************************************************************/
/*                                                                     */
/*  In the first register, UMR1 is for reads and UMR2 is for writes.   */
/*                                                                     */
/***********************************************************************/

#define MCF5307_UART_UMR1_RXRTS           (0x80)  /* Receive Request-to-Send  */
#define MCF5307_UART_UMR1_RXIRQ           (0x40)  /* Receive Interrupt Select */
#define MCF5307_UART_UMR1_ERR             (0x20)  /* Error Mode     */
#define MCF5307_UART_UMR1_PM_MULTI_ADDR   (0x1C)  /* Parity: Multidrop Adr Char */
#define MCF5307_UART_UMR1_PM_MULTI_DATA   (0x18)  /* Parity: Multidrop Data Char  */
#define MCF5307_UART_UMR1_PM_NONE         (0x10)  /* Parity: None     */
#define MCF5307_UART_UMR1_PM_FORCE_HI     (0x0C)  /* Parity: Force High   */
#define MCF5307_UART_UMR1_PM_FORCE_LO     (0x08)  /* Parity: Force Low    */
#define MCF5307_UART_UMR1_PM_ODD          (0x04)  /* Parity: Odd Parity   */
#define MCF5307_UART_UMR1_PM_EVEN         (0x00)  /* Parity: Even Parity    */
#define MCF5307_UART_UMR1_BC_5            (0x00)  /* 5 Bits Per Character   */
#define MCF5307_UART_UMR1_BC_6            (0x01)  /* 6 Bits Per Character   */
#define MCF5307_UART_UMR1_BC_7            (0x02)  /* 7 Bits Per Character   */
#define MCF5307_UART_UMR1_BC_8            (0x03)  /* 8 Bits Per Character   */

#define MCF5307_UART_UMR2_CM_NORMAL       (0x00)  /* Normal Channel Mode    */
#define MCF5307_UART_UMR2_CM_ECHO         (0x40)  /* Automatic Echo Channel Mode  */
#define MCF5307_UART_UMR2_CM_LOCAL_LOOP   (0x80)  /* Local Loopback Channel Mode  */
#define MCF5307_UART_UMR2_CM_REMOTE_LOOP  (0xC0)  /* Remote Loopback Channel Mode */
#define MCF5307_UART_UMR2_TXRTS           (0x20)  /* Transmitter Ready-to-Send  */
#define MCF5307_UART_UMR2_TXCTS           (0x10)  /* Transmitter Clear-to-Send  */
#define MCF5307_UART_UMR2_STOP_BITS_1     (0x07)  /* 1 Stop Bits      */
#define MCF5307_UART_UMR2_STOP_BITS_15    (0x08)  /* 1.5 Stop Bits      */
#define MCF5307_UART_UMR2_STOP_BITS_2     (0x0F)  /* 2 Stop Bits      */
#define MCF5307_UART_UMR2_STOP_BITS(a)    ((a)&0x0f)  /* Stop Bit Length  */

/***********************************************************************/
/*                                                                     */
/*  In this next register, USR is for reads and UCSR is for writes.    */
/*                                                                     */
/***********************************************************************/

#define MCF5307_UART_USR_RB               (0x80)  /* Received Break   */
#define MCF5307_UART_USR_FE               (0x40)  /* Framing Error    */
#define MCF5307_UART_USR_PE               (0x20)  /* Parity Error     */
#define MCF5307_UART_USR_OE               (0x10)  /* Overrun Error    */
#define MCF5307_UART_USR_TXEMP            (0x08)  /* Transmitter Empty    */
#define MCF5307_UART_USR_TXRDY            (0x04)  /* Transmitter Ready    */
#define MCF5307_UART_USR_FFULL            (0x02)  /* FIFO Full      */
#define MCF5307_UART_USR_RXRDY            (0x01)  /* Receiver Ready   */

#define MCF5307_UART_UCSR_9600_BPS        (0xBB)  /* 9600 Baud w/ 3.6864 MHz clk  */
#define MCF5307_UART_UCSR_RCS(a)          (((a)&0x0f)<<4) /* Receiver Clk Select  */
#define MCF5307_UART_UCSR_TCS(a)          ((a)&0x0f) /* Transmitter Clock Select  */

/***********************************************************************/
/*                                                                     */
/*  In this next register, there is only UCR is for writes.            */
/*                                                                     */
/***********************************************************************/

#define MCF5307_UART_UCR_NONE             (0x00)  /* No Command     */
#define MCF5307_UART_UCR_STOP_BREAK       (0x70)  /* Stop Break     */
#define MCF5307_UART_UCR_START_BREAK      (0x60)  /* Start Break      */
#define MCF5307_UART_UCR_RESET_BKCHGINT   (0x50)  /* Reset Break-Change Interrupt */
#define MCF5307_UART_UCR_RESET_ERROR      (0x40)  /* Reset Error Status   */
#define MCF5307_UART_UCR_RESET_TX         (0x30)  /* Reset Transmitter    */
#define MCF5307_UART_UCR_RESET_RX         (0x20)  /* Reset Receiver   */
#define MCF5307_UART_UCR_RESET_MR         (0x10)  /* Reset Mode Register Pointer  */
#define MCF5307_UART_UCR_TX_DISABLED      (0x08)  /* Transmitter Disabled   */
#define MCF5307_UART_UCR_TX_ENABLED       (0x04)  /* Transmitter Enabled    */
#define MCF5307_UART_UCR_RX_DISABLED      (0x02)  /* Receiver Disabled    */
#define MCF5307_UART_UCR_RX_ENABLED       (0x01)  /* Receiver Enabled   */

/***********************************************************************/
/*                                                                     */
/*  In this next register, UIPCR is for reads and UACR is for writes.  */
/*                                                                     */
/***********************************************************************/

#define MCF5307_UART_UIPCR_COS            (0x10)  /* Change-of-State at IPx input */
#define MCF5307_UART_UIPCR_CTS            (0x01)  /* Current State of CTS pin */

#define MCF5307_UART_UACR_BRG             (0x80)  /* Set 2 of Baud Rate Generator */
#define MCF5307_UART_UACR_CTMS_TIMER      (0x60)  /* Timer Mode and Source Select */
                                                  /* Must set this mode and src */
#define MCF5307_UART_UACR_IEC             (0x01)  /* Input Enable Control   */

/***********************************************************************/
/*                                                                     */
/*  In this next register, UISR is for reads and UIMR is for writes.   */
/*                                                                     */
/***********************************************************************/

#define MCF5307_UART_UISR_COS             (0x80)  /* Change-of-State at CTS input */
#define MCF5307_UART_UISR_DB              (0x04)  /* Receiver Has Detected Break  */
#define MCF5307_UART_UISR_RXRDY           (0x02)  /* Receiver Ready or FIFO Full  */
#define MCF5307_UART_UISR_TXRDY           (0x01)  /* Transmitter Ready    */

#define MCF5307_UART_UIMR_COS             (0x80)  /* Enable Change-of-State Intpt */
#define MCF5307_UART_UIMR_DB              (0x04)  /* Enable Delta Break Interrupt */
#define MCF5307_UART_UIMR_FFULL           (0x02)  /* Enable FIFO Full Interrupt */
#define MCF5307_UART_UIMR_TXRDY           (0x01)  /* Enable Transmitter Rdy Intpt */

/*******************************************************************************/
/*                                                                             */
/*  The last few registers can only be accessed as a read or write register.   */
/*                                                                             */
/*******************************************************************************/

#define MCF5307_UART_UIP_CTS              (0x01) /* Current State of CTS Input  */

#define MCF5307_UART_UOP_RTS              (0x01) /* Sets All Bits on OP Bit Set */
#define MCF5307_UART_UOP0_RTS             (0x01) /* Clears All Bits on OP Bit Rst */


/* ColdFire version independent versions */
#define MCF5XXX_UART_UMR1_RXRTS           MCF5307_UART_UMR1_RXRTS
#define MCF5XXX_UART_UMR1_RXIRQ           MCF5307_UART_UMR1_RXIRQ
#define MCF5XXX_UART_UMR1_ERR             MCF5307_UART_UMR1_ERR
#define MCF5XXX_UART_UMR1_PM_MULTI_ADDR   MCF5307_UART_UMR1_PM_MULTI_ADDR
#define MCF5XXX_UART_UMR1_PM_MULTI_DATA   MCF5307_UART_UMR1_PM_MULTI_DATA
#define MCF5XXX_UART_UMR1_PM_NONE         MCF5307_UART_UMR1_PM_NONE
#define MCF5XXX_UART_UMR1_PM_FORCE_HI     MCF5307_UART_UMR1_PM_FORCE_HI
#define MCF5XXX_UART_UMR1_PM_FORCE_LO     MCF5307_UART_UMR1_PM_FORCE_LO
#define MCF5XXX_UART_UMR1_PM_ODD          MCF5307_UART_UMR1_PM_ODD
#define MCF5XXX_UART_UMR1_PM_EVEN         MCF5307_UART_UMR1_PM_EVEN
#define MCF5XXX_UART_UMR1_BC_5            MCF5307_UART_UMR1_BC_5
#define MCF5XXX_UART_UMR1_BC_6            MCF5307_UART_UMR1_BC_6
#define MCF5XXX_UART_UMR1_BC_7            MCF5307_UART_UMR1_BC_7
#define MCF5XXX_UART_UMR1_BC_8            MCF5307_UART_UMR1_BC_8

#define MCF5XXX_UART_UMR2_CM_NORMAL       MCF5307_UART_UMR2_CM_NORMAL
#define MCF5XXX_UART_UMR2_CM_ECHO         MCF5307_UART_UMR2_CM_ECHO
#define MCF5XXX_UART_UMR2_CM_LOCAL_LOOP   MCF5307_UART_UMR2_CM_LOCAL_LOOP
#define MCF5XXX_UART_UMR2_CM_REMOTE_LOOP  MCF5307_UART_UMR2_CM_REMOTE_LOOP
#define MCF5XXX_UART_UMR2_TXRTS           MCF5307_UART_UMR2_TXRTS
#define MCF5XXX_UART_UMR2_TXCTS           MCF5307_UART_UMR2_TXCTS
#define MCF5XXX_UART_UMR2_STOP_BITS_1     MCF5307_UART_UMR2_STOP_BITS_1
#define MCF5XXX_UART_UMR2_STOP_BITS_15    MCF5307_UART_UMR2_STOP_BITS_15
#define MCF5XXX_UART_UMR2_STOP_BITS_2     MCF5307_UART_UMR2_STOP_BITS_2
#define MCF5XXX_UART_UMR2_STOP_BITS(a)    MCF5307_UART_UMR2_STOP_BITS(a)

#define MCF5XXX_UART_USR_RB               MCF5307_UART_USR_RB
#define MCF5XXX_UART_USR_FE               MCF5307_UART_USR_FE
#define MCF5XXX_UART_USR_PE               MCF5307_UART_USR_PE
#define MCF5XXX_UART_USR_OE               MCF5307_UART_USR_OE
#define MCF5XXX_UART_USR_TXEMP            MCF5307_UART_USR_TXEMP
#define MCF5XXX_UART_USR_TXRDY            MCF5307_UART_USR_TXRDY
#define MCF5XXX_UART_USR_FFULL            MCF5307_UART_USR_FFULL
#define MCF5XXX_UART_USR_RXRDY            MCF5307_UART_USR_RXRDY  

#define MCF5XXX_UART_UCSR_9600_BPS        MCF5307_UART_UCSR_9600_BPS
#define MCF5XXX_UART_UCSR_RCS(a)          MCF5307_UART_UCSR_RCS(a)
#define MCF5XXX_UART_UCSR_TCS(a)          MCF5307_UART_UCSR_TCS(a)

#define MCF5XXX_UART_UCR_NONE             MCF5307_UART_UCR_NONE
#define MCF5XXX_UART_UCR_STOP_BREAK       MCF5307_UART_UCR_STOP_BREAK
#define MCF5XXX_UART_UCR_START_BREAK      MCF5307_UART_UCR_START_BREAK
#define MCF5XXX_UART_UCR_RESET_BKCHGINT   MCF5307_UART_UCR_RESET_BKCHGINT 
#define MCF5XXX_UART_UCR_RESET_ERROR      MCF5307_UART_UCR_RESET_ERROR
#define MCF5XXX_UART_UCR_RESET_TX         MCF5307_UART_UCR_RESET_TX
#define MCF5XXX_UART_UCR_RESET_RX         MCF5307_UART_UCR_RESET_RX
#define MCF5XXX_UART_UCR_RESET_MR         MCF5307_UART_UCR_RESET_MR
#define MCF5XXX_UART_UCR_TX_DISABLED      MCF5307_UART_UCR_TX_DISABLED
#define MCF5XXX_UART_UCR_TX_ENABLED       MCF5307_UART_UCR_TX_ENABLED
#define MCF5XXX_UART_UCR_RX_DISABLED      MCF5307_UART_UCR_RX_DISABLED
#define MCF5XXX_UART_UCR_RX_ENABLED       MCF5307_UART_UCR_RX_ENABLED

#define MCF5XXX_UART_UIPCR_COS            MCF5307_UART_UIPCR_COS
#define MCF5XXX_UART_UIPCR_CTS            MCF5307_UART_UIPCR_CTS

#define MCF5XXX_UART_UACR_BRG             MCF5307_UART_UACR_BRG
#define MCF5XXX_UART_UACR_CTMS_TIMER      MCF5307_UART_UACR_CTMS_TIMER
#define MCF5XXX_UART_UACR_IEC             MCF5307_UART_UACR_IEC

#define MCF5XXX_UART_UISR_COS             MCF5307_UART_UISR_COS
#define MCF5XXX_UART_UISR_DB              MCF5307_UART_UISR_DB
#define MCF5XXX_UART_UISR_RXRDY           MCF5307_UART_UISR_RXRDY
#define MCF5XXX_UART_UISR_TXRDY           MCF5307_UART_UISR_TXRDY

#define MCF5XXX_UART_UIMR_COS             MCF5307_UART_UIMR_COS
#define MCF5XXX_UART_UIMR_DB              MCF5307_UART_UIMR_DB 
#define MCF5XXX_UART_UIMR_FFULL           MCF5307_UART_UIMR_FFULL
#define MCF5XXX_UART_UIMR_TXRDY           MCF5307_UART_UIMR_TXRDY

#define MCF5XXX_UART_UIP_CTS              MCF5307_UART_UIP_CTS 

#define MCF5XXX_UART_UOP_RTS              MCF5307_UART_UOP_RTS 
#define MCF5XXX_UART_UOP0_RTS             MCF5307_UART_UOP0_RTS   


typedef struct
{
  unsigned8 umr;          /* UARTx Mode Register, 8-bit, R/W (00) */
  unsigned8 pack01[3];    /* 01-03 */
  unsigned8 usr;          /* UARTx Status Register, 8-bit, R (04) */
  unsigned8 pack02[7];    /* 05-0B */
  unsigned8 urbuf;        /* UARTx Receiver Buffer, 8-bit, R (0C) */
  unsigned8 pack03[3];    /* 0D-0F */
  unsigned8 uipcr;        /* UARTx Input Port Change Register, 8-bit, R (10) */
  unsigned8 pack04[3];    /* 11-13 */
  unsigned8 uisr;         /* UARTx Interrupt Status Register, 8-bit, R (14) */
  unsigned8 pack05[3];    /* 15-17 */
  unsigned8 ubg1;         /* UARTx Baud Rate Generator PreScale MSB, 8-bit, R/W (18) */
  unsigned8 pack06[3];    /* 19-1B */
  unsigned8 ubg2;         /* UARTx Baud Rate Generator PreScale LSB, 8-bit, R/W (1C) */
  unsigned8 pack07[19];   /* 1D-2F */
  unsigned8 uivr;         /* UARTx Interrupt Vector Register, 8-bit, R/W (30) */
  unsigned8 pack08[3];    /* 31-33 */
  unsigned8 uip;          /* UARTx Input Port Register, 8-bit, R (34) */
} UARTReadStruct;

typedef struct
{
  unsigned8 umr;          /* UARTx Mode Register, 8-bit, R/W (00) */
  unsigned8 pack01[3];    /* 01-03 */
  unsigned8 ucsr;         /* UART1 Clock Select Register, 8-bit, W (04) */
  unsigned8 pack02[3];    /* 05-07 */
  unsigned8 ucr;          /* UARTx Command Register, 8-bit, W (08) */
  unsigned8 pack2a[3];    /* 09-0B */
  unsigned8 utbuf;        /* UARTx Transmitter Buffer, 8-bit, W (0C) */
  unsigned8 pack03[3];    /* 0D-0F */
  unsigned8 uacr;         /* UARTx Auxiliary Control Register, 8-bit, W (10) */
  unsigned8 pack04[3];    /* 11-13 */
  unsigned8 uimr;         /* UARTx Interrupt Mask Register, 8-bit, W (14) */
  unsigned8 pack05[3];    /* 15-17 */
  unsigned8 ubg1;         /* UARTx Baud Rate Generator PreScale MSB, 8-bit, R/W (18) */
  unsigned8 pack06[3];    /* 19-1B */
  unsigned8 ubg2;         /* UARTx Baud Rate Generator PreScale LSB, 8-bit, R/W (1C) */
  unsigned8 pack07[19];   /* 1D-2F */
  unsigned8 uivr;         /* UARTx Interrupt Vector Register, 8-bit, R/W (30) */
  unsigned8 pack08[7];    /* 31-37 */
  unsigned8 uop1;         /* UARTx Output Port Bit Set Command, 8-bit, W (38) */
  unsigned8 pack09[3];    /* 39-3B */
  unsigned8 uop0;         /* UARTx Output Port Bit Reset Command, 8-bit, W (3C) */
} UARTWriteStruct;

typedef union
{
  UARTReadStruct  read;
  UARTWriteStruct write; 
  unsigned8 pack01[0x40];  
} uartstruct;


#define MCF5307_MBUS_MADR_ADDR(a) (((a)&0xFE)<<0x01) /* Slave Address */

#define MCF5307_MBUS_MFDR_MBC(a)  ((a)&0x3F)  /* M-Bus Clock Rate */

#define MCF5307_MBUS_MBCR_MEN     (0x80)  /* M-Bus Enable     */
#define MCF5307_MBUS_MBCR_MIEN    (0x40)  /* M-Bus Interrupt Enable */
#define MCF5307_MBUS_MBCR_MSTA    (0x20)  /* Master/Slave Mode Select Bit */
#define MCF5307_MBUS_MBCR_MTX     (0x10)  /* Transmit/Rcv Mode Select Bit */
#define MCF5307_MBUS_MBCR_TXAK    (0x08)  /* Transmit Acknowledge Enable  */
#define MCF5307_MBUS_MBCR_RSTA    (0x04)  /* Repeat Start     */

#define MCF5307_MBUS_MBSR_MCF     (0x80)  /* Data Transfer Complete */
#define MCF5307_MBUS_MBSR_MAAS    (0x40)  /* Addressed as a Slave   */
#define MCF5307_MBUS_MBSR_MBB     (0x20)  /* Bus Busy     */
#define MCF5307_MBUS_MBSR_MAL     (0x10)  /* Arbitration Lost   */
#define MCF5307_MBUS_MBSR_SRW     (0x04)  /* Slave Transmit   */
#define MCF5307_MBUS_MBSR_MIF     (0x02)  /* M-Bus Interrupt    */
#define MCF5307_MBUS_MBSR_RXAK    (0x01)  /* No Acknowledge Received  */


/* ColdFire version independent versions */
#define MCF5XXX_MBUS_MADR_ADDR(a) MCF5307_MBUS_MADR_ADDR(a)

#define MCF5XXX_MBUS_MFDR_MBC(a)  MCF5307_MBUS_MFDR_MBC(a)

#define MCF5XXX_MBUS_MBCR_MEN     MCF5307_MBUS_MBCR_MEN 
#define MCF5XXX_MBUS_MBCR_MIEN    MCF5307_MBUS_MBCR_MIEN 
#define MCF5XXX_MBUS_MBCR_MSTA    MCF5307_MBUS_MBCR_MSTA 
#define MCF5XXX_MBUS_MBCR_MTX     MCF5307_MBUS_MBCR_MTX 
#define MCF5XXX_MBUS_MBCR_TXAK    MCF5307_MBUS_MBCR_TXAK 
#define MCF5XXX_MBUS_MBCR_RSTA    MCF5307_MBUS_MBCR_RSTA 

#define MCF5XXX_MBUS_MBSR_MCF     MCF5307_MBUS_MBSR_MCF  
#define MCF5XXX_MBUS_MBSR_MAAS    MCF5307_MBUS_MBSR_MAAS  
#define MCF5XXX_MBUS_MBSR_MBB     MCF5307_MBUS_MBSR_MBB 
#define MCF5XXX_MBUS_MBSR_MAL     MCF5307_MBUS_MBSR_MAL  
#define MCF5XXX_MBUS_MBSR_SRW     MCF5307_MBUS_MBSR_SRW
#define MCF5XXX_MBUS_MBSR_MIF     MCF5307_MBUS_MBSR_MIF
#define MCF5XXX_MBUS_MBSR_RXAK    MCF5307_MBUS_MBSR_RXAK

typedef struct
{
  unsigned8 madr;         /* M-BUS Address Register, 8-bit, R/W (00) */
  unsigned8 pack01[3];    /* 01-03 */
  unsigned8 mfdr;         /* M-BUS Frequency Divider Register, 8-bit, R/W (04) */
  unsigned8 pack02[3];    /* 05-07 */
  unsigned8 mbcr;         /* M-BUS Control Register, 8-bit, R/W (08) */
  unsigned8 pack03[3];    /* 09-0B */
  unsigned8 mbsr;         /* M-BUS Status Register, 8-bit, R/W (0C) */
  unsigned8 pack04[3];    /* 0D-0F */
  unsigned8 mbdr;         /* M-BUS Data I/O Register, 8-bit, R/W (10) */
} mbusstruct;


/* DMA Channel */
#define MCF5307_DMA_DCR_INT         (0x8000) /* Interrupt on Completion */
#define MCF5307_DMA_DCR_EEXT        (0x4000) /* Enable External Request */
#define MCF5307_DMA_DCR_CS          (0x2000) /* Cycle Steal     */
#define MCF5307_DMA_DCR_AA          (0x1000) /* Auto Align      */
#define MCF5307_DMA_DCR_BWC_DMA     (0x0000) /* Bandwidth: DMA Priority */
#define MCF5307_DMA_DCR_BWC_512     (0x0200) /* Bandwidth:   512 Bytes  */
#define MCF5307_DMA_DCR_BWC_1024    (0x0400) /* Bandwidth:  1024 Bytes  */
#define MCF5307_DMA_DCR_BWC_2048    (0x0600) /* Bandwidth:  2048 Bytes  */
#define MCF5307_DMA_DCR_BWC_4096    (0x0800) /* Bandwidth:  4096 Bytes  */
#define MCF5307_DMA_DCR_BWC_8192    (0x0a00) /* Bandwidth:  8192 Bytes  */
#define MCF5307_DMA_DCR_BWC_16384   (0x0c00) /* Bandwidth: 16384 Bytes  */
#define MCF5307_DMA_DCR_BWC_32768   (0x0e00) /* Bandwidth: 32768 Bytes  */
#define MCF5307_DMA_DCR_SAA         (0x0100) /* Single Address Access */
#define MCF5307_DMA_DCR_SRW         (0x0080) /* Forces MRW Signal High  */
#define MCF5307_DMA_DCR_SINC        (0x0040) /* Source Increment    */
#define MCF5307_DMA_DCR_SSIZE_LONG  (0x0000) /* Source Size:  Longword  */
#define MCF5307_DMA_DCR_SSIZE_BYTE  (0x0010) /* Source Size:  Byte    */
#define MCF5307_DMA_DCR_SSIZE_WORD  (0x0020) /* Source Size:  Word    */
#define MCF5307_DMA_DCR_SSIZE_LINE  (0x0030) /* Source Size:  Line    */
#define MCF5307_DMA_DCR_DINC        (0x0008) /* Destination Increment */
#define MCF5307_DMA_DCR_DSIZE_LONG  (0x0000) /* Destination Size:  Longword */
#define MCF5307_DMA_DCR_DSIZE_BYTE  (0x0002) /* Destination Size:  Byte */
#define MCF5307_DMA_DCR_DSIZE_WORD  (0x0004) /* Destination Size:  Word */
#define MCF5307_DMA_DCR_START       (0x0001) /* Start Transfer    */

#define MCF5307_DMA_DSR_CE          (0x40)  /* Configuration Error    */
#define MCF5307_DMA_DSR_BES         (0x20)  /* Bus Error on Source    */
#define MCF5307_DMA_DSR_BED         (0x10)  /* Bus Error on Destination */
#define MCF5307_DMA_DSR_REQ         (0x04)  /* Request      */
#define MCF5307_DMA_DSR_BSY         (0x02)  /* Busy       */
#define MCF5307_DMA_DSR_DONE        (0x01)  /* Transaction Done   */


/* ColdFire version independent versions */
#define MCF5XXX_DMA_DCR_INT         MCF5307_DMA_DCR_INT 
#define MCF5XXX_DMA_DCR_EEXT        MCF5307_DMA_DCR_EEXT  
#define MCF5XXX_DMA_DCR_CS          MCF5307_DMA_DCR_CS    
#define MCF5XXX_DMA_DCR_AA          MCF5307_DMA_DCR_AA  
#define MCF5XXX_DMA_DCR_BWC_DMA     MCF5307_DMA_DCR_BWC_DMA   
#define MCF5XXX_DMA_DCR_BWC_512     MCF5307_DMA_DCR_BWC_512 
#define MCF5XXX_DMA_DCR_BWC_1024    MCF5307_DMA_DCR_BWC_1024
#define MCF5XXX_DMA_DCR_BWC_2048    MCF5307_DMA_DCR_BWC_2048 
#define MCF5XXX_DMA_DCR_BWC_4096    MCF5307_DMA_DCR_BWC_4096  
#define MCF5XXX_DMA_DCR_BWC_8192    MCF5307_DMA_DCR_BWC_8192   
#define MCF5XXX_DMA_DCR_BWC_16384   MCF5307_DMA_DCR_BWC_16384 
#define MCF5XXX_DMA_DCR_BWC_32768   MCF5307_DMA_DCR_BWC_32768  
#define MCF5XXX_DMA_DCR_SAA         MCF5307_DMA_DCR_SAA 
#define MCF5XXX_DMA_DCR_SRW         MCF5307_DMA_DCR_SRW    
#define MCF5XXX_DMA_DCR_SINC        MCF5307_DMA_DCR_SINC   
#define MCF5XXX_DMA_DCR_SSIZE_LONG  MCF5307_DMA_DCR_SSIZE_LONG
#define MCF5XXX_DMA_DCR_SSIZE_BYTE  MCF5307_DMA_DCR_SSIZE_BYTE 
#define MCF5XXX_DMA_DCR_SSIZE_WORD  MCF5307_DMA_DCR_SSIZE_WORD
#define MCF5XXX_DMA_DCR_SSIZE_LINE  MCF5307_DMA_DCR_SSIZE_LINE
#define MCF5XXX_DMA_DCR_DINC        MCF5307_DMA_DCR_DINC
#define MCF5XXX_DMA_DCR_DSIZE_LONG  MCF5307_DMA_DCR_DSIZE_LONG 
#define MCF5XXX_DMA_DCR_DSIZE_BYTE  MCF5307_DMA_DCR_DSIZE_BYTE 
#define MCF5XXX_DMA_DCR_DSIZE_WORD  MCF5307_DMA_DCR_DSIZE_WORD
#define MCF5XXX_DMA_DCR_START       MCF5307_DMA_DCR_START

#define MCF5XXX_DMA_DSR_CE          MCF5307_DMA_DSR_CE
#define MCF5XXX_DMA_DSR_BES         MCF5307_DMA_DSR_BES
#define MCF5XXX_DMA_DSR_BED         MCF5307_DMA_DSR_BED
#define MCF5XXX_DMA_DSR_REQ         MCF5307_DMA_DSR_REQ 
#define MCF5XXX_DMA_DSR_BSY         MCF5307_DMA_DSR_BSY  
#define MCF5XXX_DMA_DSR_DONE        MCF5307_DMA_DSR_DONE  

typedef struct
{
  unsigned32 sar;         /* DMA Source Address Register, 32-bit, R/W (00-03) */
  unsigned32 dar;         /* DMA Destination Address Register, 32-bit, R/W (04-07) */
  unsigned16 dcr;         /* DMA Control Register, 16-bit, R/W (08-09) */
  unsigned8  pack01[2];   /* 0A-0B */
  unsigned16 bcr;         /* DMA Byte Count Regsiter, 16-bit, R/W (0C-0D) */
  unsigned8  pack02[2];   /* 0E-0F */
  unsigned8  dsr;         /* DMA Status Register, 8-bit, R/W (10) */
  unsigned8  pack03[3];   /* 11-13 */
  unsigned8  divr;        /* DMA Interrupt Vector Register, 8-bit, R/W (14) */
  unsigned8  pack04[0x2B];/* 15-3F */
} dmastruct;


/* System Integration Module */

#define MCF5307_SIM_RSR_HRST    (0x80)  /* Hard or System Reset       */
#define MCF5307_SIM_RSR_SWTR    (0x20)  /* Software Watchdog Timer Reset    */

#define MCF5307_SIM_SYPCR_SWE   (0x80)  /* Software Watchdog Enable     */
#define MCF5307_SIM_SYPCR_SWRI    (0x40)  /* SW Reset/Interrupt Select      */
#define MCF5307_SIM_SYPCR_SWT_2_9 (0x00)  /* SW Timeout: 2^9  / Sys Freq      */
#define MCF5307_SIM_SYPCR_SWT_2_11  (0x08)  /* SW Timeout: 2^11 / Sys Freq      */
#define MCF5307_SIM_SYPCR_SWT_2_13  (0x10)  /* SW Timeout: 2^13 / Sys Freq      */
#define MCF5307_SIM_SYPCR_SWT_2_15  (0x18)  /* SW Timeout: 2^15 / Sys Freq      */
#define MCF5307_SIM_SYPCR_SWT_2_18  (0x20)  /* SW Timeout: 2^18 / Sys Freq      */
#define MCF5307_SIM_SYPCR_SWT_2_20  (0x28)  /* SW Timeout: 2^20 / Sys Freq      */
#define MCF5307_SIM_SYPCR_SWT_2_22  (0x30)  /* SW Timeout: 2^22 / Sys Freq      */
#define MCF5307_SIM_SYPCR_SWT_2_24  (0x38)  /* SW Timeout: 2^24 / Sys Freq      */
#define MCF5307_SIM_SYPCR_SWTA    (0x04)  /* SW Transfer Acknowledge Enable   */
#define MCF5307_SIM_SYPCR_SWTAVAL (0x02)  /* SW Transfer Acknowledge Valid    */

#define MCF5307_SIM_SWSR_55   (0x55)    /* Write $55 to SWSR      */
#define MCF5307_SIM_SWSR_AA   (0xaa)    /* Write $AA to SWSR      */

#define MCF5307_SIM_PAR_ADDR31    (0x8000)  /* Assign Pin as ADDR31     */
#define MCF5307_SIM_PAR_ADDR30    (0x4000)  /* Assign Pin as ADDR30     */
#define MCF5307_SIM_PAR_ADDR29    (0x2000)  /* Assign Pin as ADDR29     */
#define MCF5307_SIM_PAR_ADDR28    (0x1000)  /* Assign Pin as ADDR28     */
#define MCF5307_SIM_PAR_ADDR27    (0x0800)  /* Assign Pin as ADDR27     */
#define MCF5307_SIM_PAR_ADDR26    (0x0400)  /* Assign Pin as ADDR26     */
#define MCF5307_SIM_PAR_ADDR25    (0x0200)  /* Assign Pin as ADDR25     */
#define MCF5307_SIM_PAR_ADDR24    (0x0100)  /* Assign Pin as ADDR24     */
#define MCF5307_SIM_PAR_XTIP    (0x0080)  /* Assign Pin as XTIP     */
#define MCF5307_SIM_PAR_DREQ0   (0x0040)  /* Assign Pin as DREQ0      */
#define MCF5307_SIM_PAR_DREQ1   (0x0020)  /* Assign Pin as DREQ1      */
#define MCF5307_SIM_PAR_TM2   (0x0010)  /* Assign Pin as TM2      */
#define MCF5307_SIM_PAR_TM1   (0x0008)  /* Assign Pin as TM1      */
#define MCF5307_SIM_PAR_TM0   (0x0004)  /* Assign Pin as TM0      */
#define MCF5307_SIM_PAR_TT1   (0x0002)  /* Assign Pin as TT1      */
#define MCF5307_SIM_PAR_TT0   (0x0001)  /* Assign Pin as TT0      */

#define MCF5307_SIM_IRQPAR_2    (0x80)  /* IRQ[5] pin to Int IL 4, not 5    */
#define MCF5307_SIM_IRQPAR_1    (0x20)  /* IRQ[3] pin to Int IL 6, not 3    */
#define MCF5307_SIM_IRQPAR_0    (0x10)  /* IRQ[1] pin to Int IL 2, not 1    */

#define MCF5307_SIM_PLLCR_ENBSTOP (0x80)  /* Enable CPU STOP Instruction      */
#define MCF5307_SIM_PLLCR_PLLIPL(a) (((a)&0x07)<<4) /* PLL Wake-up IPL      */

#define MCF5307_SIM_MPARK_PARK(a) (((a)&0x03)<<6) /* Default Bus Master     */
#define MCF5307_SIM_MPARK_E2MCTRL (0x20)    /* EBus to MBus Arbitration */
#define MCF5307_SIM_MPARK_EARBCTRL  (0x10)    /* SBus to EBus Arbitration */
#define MCF5307_SIM_MPARK_SHOWDATA  (0x08)    /* Show SBus on EBus      */

#define MCF5307_SIM_IPR_DMA3    (0x00020000)  /* Interrupt Pending DMA3   */
#define MCF5307_SIM_IPR_DMA2    (0x00010000)  /* Interrupt Pending DMA2   */
#define MCF5307_SIM_IPR_DMA1    (0x00008000)  /* Interrupt Pending DMA1   */
#define MCF5307_SIM_IPR_DMA0    (0x00004000)  /* Interrupt Pending DMA0   */
#define MCF5307_SIM_IPR_UART2   (0x00002000)  /* Interrupt Pending UART2  */
#define MCF5307_SIM_IPR_UART1   (0x00001000)  /* Interrupt Pending UART1  */
#define MCF5307_SIM_IPR_MBUS    (0x00000800)  /* Interrupt Pending MBUS   */
#define MCF5307_SIM_IPR_TIMER2    (0x00000400)  /* Interrupt Pending TIMER2 */
#define MCF5307_SIM_IPR_TIMER1    (0x00000200)  /* Interrupt Pending TIMER1 */
#define MCF5307_SIM_IPR_SWT   (0x00000100)  /* Interrupt Pending SWT    */
#define MCF5307_SIM_IPR_EINT7   (0x00000080)  /* Interrupt Pending EINT7  */
#define MCF5307_SIM_IPR_EINT6   (0x00000040)  /* Interrupt Pending EINT7  */
#define MCF5307_SIM_IPR_EINT5   (0x00000020)  /* Interrupt Pending EINT7  */
#define MCF5307_SIM_IPR_EINT4   (0x00000010)  /* Interrupt Pending EINT7  */
#define MCF5307_SIM_IPR_EINT3   (0x00000008)  /* Interrupt Pending EINT7  */
#define MCF5307_SIM_IPR_EINT2   (0x00000004)  /* Interrupt Pending EINT7  */
#define MCF5307_SIM_IPR_EINT1   (0x00000002)  /* Interrupt Pending EINT7  */

#define MCF5307_SIM_IMR_DMA3    (0x00020000)  /* Mask DMA3        */
#define MCF5307_SIM_IMR_DMA2    (0x00010000)  /* Mask DMA2        */
#define MCF5307_SIM_IMR_DMA1    (0x00008000)  /* Mask DMA1        */
#define MCF5307_SIM_IMR_DMA0    (0x00004000)  /* Mask DMA0        */
#define MCF5307_SIM_IMR_UART2   (0x00002000)  /* Mask UART2       */
#define MCF5307_SIM_IMR_UART1   (0x00001000)  /* Mask UART1       */
#define MCF5307_SIM_IMR_MBUS    (0x00000800)  /* Mask MBUS        */
#define MCF5307_SIM_IMR_TIMER2    (0x00000400)  /* Mask TIMER2        */
#define MCF5307_SIM_IMR_TIMER1    (0x00000200)  /* Mask TIMER1        */
#define MCF5307_SIM_IMR_SWT   (0x00000100)  /* Mask SWT       */
#define MCF5307_SIM_IMR_EINT7   (0x00000080)  /* Mask EINT7       */
#define MCF5307_SIM_IMR_EINT6   (0x00000040)  /* Mask EINT6       */
#define MCF5307_SIM_IMR_EINT5   (0x00000020)  /* Mask EINT5       */
#define MCF5307_SIM_IMR_EINT4   (0x00000010)  /* Mask EINT4       */
#define MCF5307_SIM_IMR_EINT3   (0x00000008)  /* Mask EINT3       */
#define MCF5307_SIM_IMR_EINT2   (0x00000004)  /* Mask EINT2       */
#define MCF5307_SIM_IMR_EINT1   (0x00000002)  /* Mask EINT1       */

#define MCF5307_SIM_AVCR_AVEC7    (0x80)  /* Auto Vector Ext Interrupt 7      */
#define MCF5307_SIM_AVCR_AVEC6    (0x40)  /* Auto Vector Ext Interrupt 6      */
#define MCF5307_SIM_AVCR_AVEC5    (0x20)  /* Auto Vector Ext Interrupt 5      */
#define MCF5307_SIM_AVCR_AVEC4    (0x10)  /* Auto Vector Ext Interrupt 4      */
#define MCF5307_SIM_AVCR_AVEC3    (0x08)  /* Auto Vector Ext Interrupt 3      */
#define MCF5307_SIM_AVCR_AVEC2    (0x04)  /* Auto Vector Ext Interrupt 2      */
#define MCF5307_SIM_AVCR_AVEC1    (0x02)  /* Auto Vector Ext Interrupt 1      */
#define MCF5307_SIM_AVCR_BLK    (0x01)  /* Block Address Strobe       */

#define MCF5307_SIM_ICR_AVEC    (0x80)    /* Autovector Enable      */
#define MCF5307_SIM_ICR_IL(a)   (((a)&0x07)<<2) /* Interrupt Level      */
#define MCF5307_SIM_ICR_IP_EXT    (0x02)    /* High Priority External   */
#define MCF5307_SIM_ICR_IP_INT    (0x01)    /* High Priority Internal   */
#define MCF5307_SIM_ICR_IP(a)   (((a)&0x03))

/***********************************************************************/
/*                                                                     */
/*  Controls used by both Synchronous and Asynchronous DRAM            */
/*                                                                     */
/***********************************************************************/

#define MCF5307_DRAMC_DCR_SO    (0x8000)  /* Synchronous Operation  */
#define MCF5307_DRAMC_DCR_NAM   (0x2000)  /* No Address Multiplexing  */
#define MCF5307_DRAMC_DCR_RC(a)   ((a)&0x01FF)  /* Refresh Count    */

#define MCF5307_DRAMC_DACR_BASE(a)  ((a)&0xFFFC0000) /* Base Address    */
#define MCF5307_DRAMC_DACR_RE   (0x00008000)  /* Refresh Enable   */
#define MCF5307_DRAMC_DACR_PS_32  (0x00000000)  /* Port Size:  32-bit   */
#define MCF5307_DRAMC_DACR_PS_8   (0x00000010)  /* Port Size:   8-bit   */
#define MCF5307_DRAMC_DACR_PS_16  (0x00000020)  /* Port Size:  16-bit   */

#define MCF5307_DRAMC_DCMR_MASK_4G  (0xFFFC0000)  /* DRAM Size of 4G    */
#define MCF5307_DRAMC_DCMR_MASK_2G  (0x7FFC0000)  /* DRAM Size of 2G    */
#define MCF5307_DRAMC_DCMR_MASK_1G  (0x3FFC0000)  /* DRAM Size of 1G    */
#define MCF5307_DRAMC_DCMR_MASK_1024M (0x3FFC0000)  /* DRAM Size of 1024M   */
#define MCF5307_DRAMC_DCMR_MASK_512M  (0x1FFC0000)  /* DRAM Size of 512M    */
#define MCF5307_DRAMC_DCMR_MASK_256M  (0x0FFC0000)  /* DRAM Size of 256M    */
#define MCF5307_DRAMC_DCMR_MASK_128M  (0x07FC0000)  /* DRAM Size of 128M    */
#define MCF5307_DRAMC_DCMR_MASK_64M (0x03FC0000)  /* DRAM Size of 64M   */
#define MCF5307_DRAMC_DCMR_MASK_32M (0x01FC0000)  /* DRAM Size of 32M   */
#define MCF5307_DRAMC_DCMR_MASK_16M (0x00FC0000)  /* DRAM Size of 16M   */
#define MCF5307_DRAMC_DCMR_MASK_8M  (0x007C0000)  /* DRAM Size of 8M    */
#define MCF5307_DRAMC_DCMR_MASK_4M  (0x003C0000)  /* DRAM Size of 4M    */
#define MCF5307_DRAMC_DCMR_MASK_2M  (0x001C0000)  /* DRAM Size of 2M    */
#define MCF5307_DRAMC_DCMR_MASK_1M  (0x000C0000)  /* DRAM Size of 1M    */
#define MCF5307_DRAMC_DCMR_MASK_1024K (0x00040000)  /* DRAM Size of 1024K   */
#define MCF5307_DRAMC_DCMR_MASK_256K  (0x00000000)  /* DRAM Size of 512K    */
#define MCF5307_DRAMC_DCMR_WP   (0x00000100)  /* Write Protect    */
#define MCF5307_DRAMC_DCMR_CPU    (0x00000040)  /* CPU Space Ignored    */
#define MCF5307_DRAMC_DCMR_AM   (0x00000020)  /* Alternate Master Ignored */
#define MCF5307_DRAMC_DCMR_SC   (0x00000010)  /* Supervisor Code Ignored  */
#define MCF5307_DRAMC_DCMR_SD   (0x00000008)  /* Supervisor Data Ignored  */
#define MCF5307_DRAMC_DCMR_UC   (0x00000004)  /* User Code Ignored    */
#define MCF5307_DRAMC_DCMR_UD   (0x00000002)  /* User Data Ignored    */
#define MCF5307_DRAMC_DCMR_V    (0x00000001)  /* Valid Register   */

/***********************************************************************/
/*                                                                     */
/*  Controls used only by Asynchronous DRAM                            */
/*                                                                     */
/***********************************************************************/

#define MCF5307_DRAMC_DCR_RRA_2   (0x0000) /* Refresh RAS Asserted 2 Clocks */
#define MCF5307_DRAMC_DCR_RRA_3   (0x0800) /* Refresh RAS Asserted 3 Clocks */
#define MCF5307_DRAMC_DCR_RRA_4   (0x1000) /* Refresh RAS Asserted 4 Clocks */
#define MCF5307_DRAMC_DCR_RRA_5   (0x1800) /* Refresh RAS Asserted 5 Clocks */
#define MCF5307_DRAMC_DCR_RRP_1   (0x0000) /* Refresh RAS Precharged 3 Clks */
#define MCF5307_DRAMC_DCR_RRP_2   (0x0200) /* Refresh RAS Precharged 3 Clks */
#define MCF5307_DRAMC_DCR_RRP_3   (0x0400) /* Refresh RAS Precharged 3 Clks */
#define MCF5307_DRAMC_DCR_RRP_4   (0x0600) /* Refresh RAS Precharged 3 Clks */

#define MCF5307_DRAMC_DACR_CAS_1  (0x00000000)  /* CAS Active 1 Clock   */
#define MCF5307_DRAMC_DACR_CAS_2  (0x00001000)  /* CAS Active 2 Clocks    */
#define MCF5307_DRAMC_DACR_CAS_3  (0x00002000)  /* CAS Active 3 Clocks    */
#define MCF5307_DRAMC_DACR_CAS_4  (0x00003000)  /* CAS Active 4 Clocks    */
#define MCF5307_DRAMC_DACR_RP_1   (0x00000000)  /* RAS Precharge 1 Clock  */
#define MCF5307_DRAMC_DACR_RP_2   (0x00000400)  /* RAS Precharge 2 Clocks */
#define MCF5307_DRAMC_DACR_RP_3   (0x00000800)  /* RAS Precharge 3 Clocks */
#define MCF5307_DRAMC_DACR_RP_4   (0x00000C00)  /* RAS Precharge 4 Clocks */
#define MCF5307_DRAMC_DACR_RNCN   (0x00000200)  /* RAS Negate to CAS Negate */
#define MCF5307_DRAMC_DACR_RCD_1  (0x00000000)  /* 1 Clock Between RAS and CAS  */
#define MCF5307_DRAMC_DACR_RCD_2  (0x00000100)  /* 2 Clocks Between RAS and CAS */
#define MCF5307_DRAMC_DACR_EDO    (0x00000040)  /* Extended Data Out    */
#define MCF5307_DRAMC_DACR_PM_OFF (0x00000000)  /* No Page Mode     */
#define MCF5307_DRAMC_DACR_PM_BURST (0x00000004)  /* Page Mode on Burst Only  */
#define MCF5307_DRAMC_DACR_PM_ON  (0x0000000C)  /* Continuous Page Mode   */

/***********************************************************************/
/*                                                                     */
/*  Controls used only by Synchronous DRAM                             */
/*                                                                     */
/***********************************************************************/

#define MCF5307_DRAMC_DCR_COC   (0x1000) /* Command on Clock Enable   */
#define MCF5307_DRAMC_DCR_IS    (0x0800) /* Initiate Self Refresh Command */
#define MCF5307_DRAMC_DCR_RTIM_3  (0x0000) /* 3 Clocks Between REF and ACTV Cmds  */
#define MCF5307_DRAMC_DCR_RTIM_6  (0x0200) /* 6 Clocks Between REF and ACTV Cmds  */
#define MCF5307_DRAMC_DCR_RTIM_9  (0x0400) /* 9 Clocks Between REF and ACTV Cmds  */

#define MCF5307_DRAMC_DACR_CASL_1 (0x00000000) /* 1 Clock From CAS to Data  */
#define MCF5307_DRAMC_DACR_CASL_2 (0x00001000) /* 2 Clock From CAS to Data  */
#define MCF5307_DRAMC_DACR_CASL_3 (0x00002000) /* 3 Clock From CAS to Data  */
#define MCF5307_DRAMC_DACR_CBM(a) (((a)&0x00000007)<<8) /* Command and Bank Mux */
#define MCF5307_DRAMC_DACR_IMRS   (0x00000040) /* Initiate Mode Register Set Cmd  */
#define MCF5307_DRAMC_DACR_IP   (0x00000008) /* Initiate Precharge All Command  */
#define MCF5307_DRAMC_DACR_PM   (0x00000004) /* Continuous Page Mode    */



typedef struct
{
  unsigned8  rsr;         /* Reset Status Register, 8-bit, R/W (000) */
  unsigned8  sypcr;       /* System Protection Control Register, 8-bit, R/W (001) */
  unsigned8  swivr;       /* Software Watchdog Interrupt Vector Register, 8-bit, W (002) */
  unsigned8  swsr;        /* Software Watchdog Service Register, 8-bit, W (003) */
  unsigned16 par;         /* Pin Assignment Register, 16-bit, R/W (004) */
  unsigned8  irqpar;      /* Interrupt Assignment Register, 8-bit, R/W (006) */
  unsigned8  pack01;      /* 007-007 */
  unsigned8  pllcr;       /* PLL Control Register, 8-bit, R/W (008) */
  unsigned8  pack02[3];   /* 009-00B */
  unsigned8  mpark;       /* Bus Master Control Register, 8-bit, R/W (00C) */
  unsigned8  pack03[0x33];/* 00D-03F */
  unsigned32 ipr;         /* Interrupt Pending Register, 32-bit, R (040-043) */
  unsigned32 imr;         /* Interrupt Mask Register, 32-bit, R/W (044-047) */
  unsigned8  pack04[3];   /* 048-04A */
  unsigned8  avcr;        /* Auto Vector Control Register, 8-bit, R/W (04B) */
  unsigned8  icr0;        /* Interrupt Control Register Ext0, 8-bit, R/W (04C) */
  unsigned8  icr1;        /* Interrupt Control Register Ext1, 8-bit, R/W (04D) */
  unsigned8  icr2;        /* Interrupt Control Register Ext2, 8-bit, R/W (04E) */
  unsigned8  icr3;        /* Interrupt Control Register Ext3, 8-bit, R/W (04F) */
  unsigned8  icr4;        /* Interrupt Control Register Ext4, 8-bit, R/W (050) */
  unsigned8  icr5;        /* Interrupt Control Register Ext5, 8-bit, R/W (051) */
  unsigned8  icr6;        /* Interrupt Control Register Ext6, 8-bit, R/W (052) */
  unsigned8  icr7;        /* Interrupt Control Register Ext7, 8-bit, R/W (053) */
  unsigned8  icr8;        /* Interrupt Control Register Ext8, 8-bit, R/W (054) */
  unsigned8  icr9;        /* Interrupt Control Register Ext9, 8-bit, R/W (055) */
  unsigned8  icr10;       /* Interrupt Control Register Ext10, 8-bit, R/W (056) */
  unsigned8  icr11;       /* Interrupt Control Register Ext11, 8-bit, R/W (057) */
  unsigned8  pack05[0x28];/* 058-07F */

/** Chip Select Registers **/
  
  csstruct_abs     cs_abs[2];    /* Absolute Chip-Select registers (080-097) */
  unsigned8        csbar;        /* Relative Chip-Select Base Register (098) */
  unsigned8        pack06[3];    /* 099-9B */
  csstruct_rel     cs_rel[6];    /* Relative Chip-Select registers (09C-0E3) */
  unsigned8        pack07[0x1C]; /* 0E4-0FF */


/** DRAM Controller Registers **/
  
  unsigned16 dcr;         /* DRAM Controller Register, 16-bit, R/W (100-101) */
  unsigned8  pack08[6];   /* 102-107 */
  
  unsigned32 dacr0;       /* DRAM Controller Bank 0 Address & Control Register, 32-bit, R/W (108-10B) */
  unsigned32 dmr0;        /* DRAM Controller Bank 0 Mask Register, 32-bit, R/W (10C-10F) */
  unsigned32 dacr1;       /* DRAM Controller Bank 1 Address & Control Register, 32-bit, R/W (110-113) */
  unsigned32 dmr1;        /* DRAM Controller Bank 1 Mask Register, 32-bit, R/W (114-117) */


/** General Purpose I/O **/

  unsigned8 pack09[0x28]; /* 118-13F */
  tmrstruct       timer1; /* Timer 1 Module (140-151) */
  unsigned8 pack10[0x2E]; /* 152-17F */
  tmrstruct       timer2; /* Timer 2 Module (180-191) */
  unsigned8 pack11[0x2E]; /* 192-1BF */
  uartstruct      uart1;  /* UART 1 Module (1C0-1FF) */
  uartstruct      uart2;  /* UART 2 Module (200-23F) */
  unsigned8 pack12[4];    /* 240-243 */
  unsigned16      paddr;  /* Port A Data Direction Register, 16-bit, R/W (244-245) */
  unsigned8 pack13[2];    /* 246-247 */
  unsigned16      padat;  /* Port A Data Direction Register, 16-bit, R/W (248-249) */
  unsigned8 pack14[0x36]; /* 24A-27F */
  mbusstruct      mbus;   /* MBUS Module (280 - 290) */
  unsigned8 pack15[0x6F]; /* 291 - 2FF */
  dmastruct       dma[4]; /* 4 DMA Channels (300 - 3FF) */

} SIM5307;


#endif /* __MCF5307_H */
